erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/brox/caboc: Enable PEG60 with PEG62

Browse source 
Currently the SSD is preventing the system from entering S0ix sleep,
the system PKG C-State is stuck at PC3.

Intel RDC#642067 reveals while PEG60 is NDA but PEG62 is DA, need to
keep default PEG60 enabled and assign an unused CLKREQ# for port PEG60.

PEG60 is 00:06.0 (CPU PCIe Root port A).
PEG62 is 00:06.2 (CPU PCIe Root port B).
Caboc connectd SSD to PEG62 while PEG60 is not used.

As described above, follow RDC to assign the unused CLKREQ#5 for port
PEG60 and enable its related settings including pcie4_0, GPP_H23 NF2
as SRCCLKREQ#5, vGPIO and confirm the SSD can enter suspend.

BUG=b:435567235
TEST= emerge-brox coreboot
      suspend_stress_test pass 100 cycles on SSD sku.
      Measured the Boot/Resume time has improved.
      seconds_power_on_to_kernel (Boot time)
      Before/After 2.616/1.609
      seconds_system_resume (Resume time)
      Before/After s0ix error/0.338123

Change-Id: I26afeffd466cb2d8e0a0e4213214bde3b0a3b25b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
This commit is contained in:
Tony Huang 2025-08-13 13:35:08 +08:00 • committed by Matt DeVillier
commit 2146ecc8e1
2 changed files with 35 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

25
src/mainboard/google/brox/variants/caboc/gpio.c
View file

@ -67,6 +67,9 @@ static const struct pad_config override_gpio_table[] = {
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
/* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L)*/
PAD_CFG_GPO(GPP_F21, 1, DEEP),
/* GPP_H23 : SRCCLKREQ5_L ==> */
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
};
/* Early pad configuration in bootblock */
@ -129,6 +132,28 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, PLTRST, NF1),
/* CPU PCIe vGPIO for PEG60 */
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
};
static const struct pad_config romstage_gpio_table[] = {

10
src/mainboard/google/brox/variants/caboc/overridetree.cb
View file

@ -233,6 +233,16 @@ chip soc/intel/alderlake
end
end
end
device ref pcie4_0 on
# Enable CPU PCIE RP 1 using CLK 5
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_req = 5,
.clk_src = 5,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
probe STORAGE STORAGE_NVME
probe unprovisioned
end
device ref pcie4_1 on
# Enable CPU PCIE RP 3 using CLK 0
register "cpu_pcie_rp[CPU_RP(3)]" = "{