vc/intel/fsp: Update PTL FSP headers to FSP 3272_04
Update header files for FSP for Panther Lake platform to FSP 3272_04
from FSP 3182_01
Details:
-Update FspmUpd.h: Add below variable
-MsHashInterleaveBit, MsHashMask, LogoPixelHeight, LogoPixelWidth,
LogoXPosition, VgaGraphicsMode12ImagePtr, LogoYPosition,
IsWckIdleExitEnabled, ChannelToCkdQckMapping, PhyClockToCkdDimm
-Update FspsUpd.h: Update the definition of PchTsnEnable
-Update MemInfoHob.h:
- Add structure for RMT_VAR and related defintions.
BUG=b:435593291
TEST=Able to build google/fatcat with the partial header changes
Change-Id: Ibd9f32798e07d53a7e0e12b5828435c6d70f5f57
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
alokagar
Subrata Banik
parent
d315f26217
commit
7c0f7e0b3f
3 changed files with 101 additions and 23 deletions
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@ -636,9 +636,12 @@ typedef struct {
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**/
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UINT8 ScramblerSupport;
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/** Offset 0x020B - Reserved
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/** Offset 0x020B - Memory Slice Hash Override
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Memory Slice (Controller) Hash Mask and LSB Override. 0 = Use default memory slice
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hash mask / lsb, 1 = Use values from MsHashMask and MsHashInterleaveBit
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$EN_DIS
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**/
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UINT8 Reserved11;
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UINT8 MsHashOverride;
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/** Offset 0x020C - Memory Voltage
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DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM
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@ -676,7 +679,7 @@ typedef struct {
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/** Offset 0x0213 - Reserved
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**/
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UINT8 Reserved12;
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UINT8 Reserved11;
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/** Offset 0x0214 - Ch Hash Override
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Select if Channel Hash setting values will be taken from input parameters or automatically
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@ -687,7 +690,7 @@ typedef struct {
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/** Offset 0x0215 - Reserved
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**/
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UINT8 Reserved13[2];
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UINT8 Reserved12[2];
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/** Offset 0x0217 - DQS Rise/Fall
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Enables/Disable DQS Rise/Fall
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@ -697,7 +700,7 @@ typedef struct {
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/** Offset 0x0218 - Reserved
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**/
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UINT8 Reserved14[2];
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UINT8 Reserved13[2];
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/** Offset 0x021A - Functional Duty Cycle Correction for DDR5 CLK
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Enable/Disable Functional Duty Cycle Correction for DDR5 CLK
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@ -729,7 +732,7 @@ typedef struct {
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/** Offset 0x021F - Reserved
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**/
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UINT8 Reserved15;
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UINT8 Reserved14;
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/** Offset 0x0220 - Functional Duty Cycle Correction for Data DQ
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Enable/Disable Functional Duty Cycle Correction for Data DQ
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@ -739,7 +742,7 @@ typedef struct {
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/** Offset 0x0221 - Reserved
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**/
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UINT8 Reserved16[5];
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UINT8 Reserved15[5];
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/** Offset 0x0226 - Unmatched Rx Calibration
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Enable/Disable Rx Unmatched Calibration
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@ -749,7 +752,24 @@ typedef struct {
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/** Offset 0x0227 - Reserved
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**/
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UINT8 Reserved17[26];
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UINT8 Reserved16[10];
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/** Offset 0x0231 - Memory Slice Hash LSB Bit
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Memory Slice (Controller) Hash LSB bit. Valid values are 0..7 for BITS 6..13; used
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when MsHashOverride is set
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0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
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**/
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UINT8 MsHashInterleaveBit;
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/** Offset 0x0232 - Memory Slice Hash Mask
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Memory Slice (Controller) Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6]
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set(Maximum); used when MsHashOverride is set
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**/
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UINT16 MsHashMask;
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/** Offset 0x0234 - Reserved
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**/
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UINT8 Reserved17[13];
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/** Offset 0x0241 - LVR Auto Trim
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Enable/disable LVR Auto Trim
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@ -1427,9 +1447,15 @@ typedef struct {
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**/
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UINT8 Use1p5ReadPostamble;
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/** Offset 0x031D - Reserved
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/** Offset 0x031D - IsWckIdleExitEnabled
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Enables/Disables WCK Idle Exit
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$EN_DIS
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**/
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UINT8 Reserved32[18];
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UINT8 IsWckIdleExitEnabled;
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/** Offset 0x031E - Reserved
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**/
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UINT8 Reserved32[17];
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/** Offset 0x032F - Board Type
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MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
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@ -2716,14 +2742,37 @@ typedef struct {
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/** Offset 0x0A71 - Control SOL VGA Initialition sequence
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Initialise SOL Init, BIT0 - (0 : Disable VGA Support, 1 : Enable VGA Support),,
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BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported,
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1: NO VGA Exit)
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1: NO VGA Exit), BIT3 - (0 : VGA Init During Display Init, 1 - VGA Init During
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MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar)
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0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA
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**/
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UINT8 VgaInitControl;
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/** Offset 0x0A72 - Reserved
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/** Offset 0x0A72 - SOL VGA Graphics Mode 12 LogoPixelHeight
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Heigh of VGA Graphics Mode 12 Logo
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**/
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UINT8 Reserved84[16];
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UINT16 LogoPixelHeight;
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/** Offset 0x0A74 - SOL VGA Graphics Mode 12 LogoPixelWidth
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Width of VGA Graphics Mode 12 Logo
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**/
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UINT16 LogoPixelWidth;
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/** Offset 0x0A76 - SOL VGA Graphics Mode 12 Image X Position
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X position of Image on Display
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**/
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UINT16 LogoXPosition;
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/** Offset 0x0A78 - SOL VGA Graphics Mode 12 Image Pointer
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Points to SOL VGA Graphics Graphics 12 Image, VgaPlanarImage200x58[4][58][25] for
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58Hx200W as example,
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**/
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UINT64 VgaGraphicsMode12ImagePtr;
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/** Offset 0x0A80 - SOL VGA Graphics Mode 12 Image Y Position
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Y position of Image on Display
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**/
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UINT16 LogoYPosition;
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/** Offset 0x0A82 - TCSS USB HOST (xHCI) Enable
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Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
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@ -2733,7 +2782,7 @@ typedef struct {
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/** Offset 0x0A83 - Reserved
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**/
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UINT8 Reserved85[4];
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UINT8 Reserved84[4];
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/** Offset 0x0A87 - TCSS Type C Port 0
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Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
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@ -2765,7 +2814,7 @@ typedef struct {
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/** Offset 0x0A8B - Reserved
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**/
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UINT8 Reserved86;
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UINT8 Reserved85;
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/** Offset 0x0A8C - TypeC port GPIO setting
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GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
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@ -2833,7 +2882,7 @@ typedef struct {
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/** Offset 0x0AC9 - Reserved
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**/
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UINT8 Reserved87;
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UINT8 Reserved86;
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/** Offset 0x0ACA - DLL Weak Lock Support
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Enables/Disable DLL Weak Lock Support
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@ -2843,7 +2892,7 @@ typedef struct {
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/** Offset 0x0ACB - Reserved
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**/
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UINT8 Reserved88;
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UINT8 Reserved87;
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/** Offset 0x0ACC - Rx DQS Delay Comp Support
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Enables/Disable Rx DQS Delay Comp Support
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@ -2853,7 +2902,7 @@ typedef struct {
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/** Offset 0x0ACD - Reserved
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**/
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UINT8 Reserved89[2];
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UINT8 Reserved88[2];
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/** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
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Enables/Disable Mrc Failure On Unsupported Dimm
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@ -2863,7 +2912,7 @@ typedef struct {
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/** Offset 0x0AD0 - Reserved
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**/
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UINT8 Reserved90[4];
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UINT8 Reserved89[4];
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/** Offset 0x0AD4 - DynamicMemoryBoost
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Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
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@ -2881,7 +2930,7 @@ typedef struct {
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/** Offset 0x0ADC - Reserved
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**/
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UINT8 Reserved91[9];
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UINT8 Reserved90[9];
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/** Offset 0x0AE5 - Vref Offset
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Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
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@ -2892,7 +2941,7 @@ typedef struct {
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/** Offset 0x0AE6 - Reserved
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**/
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UINT8 Reserved92[2];
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UINT8 Reserved91[2];
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/** Offset 0x0AE8 - tRRSG Delta
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Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
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@ -3008,7 +3057,21 @@ typedef struct {
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/** Offset 0x0AF8 - Reserved
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**/
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UINT8 Reserved93[112];
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UINT8 Reserved92[41];
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/** Offset 0x0B21 - Channel to CKD QCK Mapping
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Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
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**/
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UINT8 ChannelToCkdQckMapping[8];
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/** Offset 0x0B29 - DDRIO Clock to CKD DIMM
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Specify DDRIO Clock to CKD DIMM for CH0D0/CH0D1/CH1D0&CH1D1
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**/
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UINT8 PhyClockToCkdDimm[8];
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/** Offset 0x0B31 - Reserved
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**/
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UINT8 Reserved93[55];
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} FSP_M_CONFIG;
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/** Fsp M UPD Configuration
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@ -1667,7 +1667,9 @@ typedef struct {
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**/
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UINT16 PchTemperatureHotLevel;
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/** Offset 0x1226
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/** Offset 0x1226 - Enable PCH TSN
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Enable/disable TSN on the PCH.
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$EN_DIS
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**/
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UINT8 PchTsnEnable[4];
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@ -392,6 +392,19 @@ typedef struct {
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UINT8 *Buffer;
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} MEMORY_PLATFORM_DATA_HOB;
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#define EFI_RMT_OS_VARIABLE_NAME L"Rmt"
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#define RMT_ENABLE 1
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#define RMT_DISABLE 0
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extern EFI_GUID gRmtVariableGuid;
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//Structure of RMT UEFI variable which should be R/W by OS
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//EnDsRmt - To enable Memory margining support
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typedef struct {
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UINT8 EnDsRmt;
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} RMT_VAR;
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#pragma pack (pop)
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#endif // _MEM_INFO_HOB_H_
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