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Swathi Tamilselvan cec34128d0 soc/qualcomm/x1p42100: Support to load CPUCP firmware in x1p42100
CPUCP firmware along with its corresponding DTB must be loaded
and then taken out of reset from coreboot to initialize the CPUCP
subsystem. This patch adds support to load CPUCP and CPUCP DTB
firmware in X1P42100. The register details are part of
HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified using CPUCP load log from coreboot.
```
[INFO ]  CBFS: Found 'fallback/cpucp_dtbs' @0xe5580 size 0x163 in mcache
		 @0xff7dd714
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
		supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 355 bytes, hash algo 2, HW acceleration
		forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x81240000 memsize 0x103c srcaddr
		0x9f804130 filesize 0x12b
[DEBUG]  Loading Segment: addr: 0x81240000 memsz: 0x000000000000103c
		filesz: 0x000000000000012b
[DEBUG]  using LZMA
[SPEW ]  [ 0x81240000, 8124103c, 0x8124103c) <- 9f804130
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    Entry Point 0x81240000
[SPEW ]  Loaded segments
[DEBUG]  SOC:CPUCP DTBS image loaded successfully.
[INFO ]  CBFS: Found 'fallback/cpucp' @0xbe8c0 size 0x2607d in mcache
		@0xff7dd658
[DEBUG]  read SPI 0xcee914 0x2607d: 12635 us, 12328 KB/s, 98.624 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
		supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 155773 bytes, hash algo 2, HW
		acceleration forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x1cb00000 memsize 0x2a628 srcaddr
		0x9f8041f4 filesize 0x11c6f
[DEBUG]  Loading Segment: addr: 0x1cb00000 memsz: 0x000000000002a628
		filesz: 0x0000000000011c6f
[DEBUG]  using LZMA
[SPEW ]  [ 0x1cb00000, 1cb21950, 0x1cb2a628) <- 9f8041f4
[DEBUG]  Clearing Segment: addr: 0x000000001cb21950 memsz:
		0x0000000000008cd8
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x1cb2b000 memsize 0xb520 srcaddr
		0x9f815e63 filesize 0x134e
[DEBUG]  Loading Segment: addr: 0x1cb2b000 memsz: 0x000000000000b520
		filesz: 0x000000000000134e
[DEBUG]  using LZMA
[SPEW ]  [ 0x1cb2b000, 1cb36520, 0x1cb36520) <- 9f815e63
[DEBUG]  Loading segment from ROM address 0x9f804130
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x1cb3e000 memsize 0x890 srcaddr
		0x9f8171b1 filesize 0x23
[DEBUG]  Loading Segment: addr: 0x1cb3e000 memsz: 0x0000000000000890
		filesz: 0x0000000000000023
[DEBUG]  using LZMA
[SPEW ]  [ 0x1cb3e000, 1cb3e890, 0x1cb3e890) <- 9f8171b1
[DEBUG]  Loading segment from ROM address 0x9f80414c
[DEBUG]    BSS 0x1cb3f000 (4096 byte)
[DEBUG]  Loading Segment: addr: 0x1cb3f000 memsz: 0x0000000000001000
		filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x1cb3f000, 1cb3f000, 0x1cb40000) <- 9f8171d4
[DEBUG]  Clearing Segment: addr: 0x000000001cb3f000 memsz:
		0x0000000000001000
[DEBUG]  Loading segment from ROM address 0x9f804168
[DEBUG]    BSS 0x81200000 (38916 byte)
[DEBUG]  Loading Segment: addr: 0x81200000 memsz: 0x0000000000009804
		filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x81200000, 81200000, 0x81209804) <- 9f8171d4
[DEBUG]  Clearing Segment: addr: 0x0000000081200000 memsz:
		0x0000000000009804
[DEBUG]  Loading segment from ROM address 0x9f804184
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x81250000 memsize 0x11068 srcaddr
		0x9f8171d4 filesize 0xe59
[DEBUG]  Loading Segment: addr: 0x81250000 memsz: 0x0000000000011068
		filesz: 0x0000000000000e59
[DEBUG]  using LZMA
[SPEW ]  [ 0x81250000, 81261068, 0x81261068) <- 9f8171d4
[DEBUG]  Loading segment from ROM address 0x9f8041a0
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x81280000 memsize 0xc628 srcaddr
		0x9f81802d filesize 0x6d09
[DEBUG]  Loading Segment: addr: 0x81280000 memsz: 0x000000000000c628
		filesz: 0x0000000000006d09
[DEBUG]  using LZMA
[SPEW ]  [ 0x81280000, 8128c628, 0x8128c628) <- 9f81802d
[DEBUG]  Loading segment from ROM address 0x9f8041bc
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x81290000 memsize 0x31bf8 srcaddr
		0x9f81ed36 filesize 0xb43f
[DEBUG]  Loading Segment: addr: 0x81290000 memsz: 0x0000000000031bf8
		filesz: 0x000000000000b43f
[DEBUG]  using LZMA
[SPEW ]  [ 0x81290000, 812c1bf8, 0x812c1bf8) <- 9f81ed36
[DEBUG]  Loading segment from ROM address 0x9f8041d8
[DEBUG]    Entry Point 0x1cb00000
[SPEW ]  Loaded segments
[DEBUG]  SOC:CPUCP image loaded successfully.
[DEBUG]  CPU_CLUSTER: 0 init finished in 735 msecs
```

Change-Id: I195f038b2380de7796691f0194cf3e39f8d9a991
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88815
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-08-21 07:11:20 +00:00
3rdparty Update arm-trusted-firmware submodule to upstream master 2025-06-07 04:17:09 +00:00
configs mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM 2025-08-11 15:21:19 +00:00
Documentation Doc/contributing: Add clarification on how to reference other commits 2025-08-19 20:57:21 +00:00
LICENSES LICENSES: Add LGPL 2.1 license 2024-02-18 01:56:38 +00:00
payloads payload/seabios: Update from 1.16.3 to 1.17.0 2025-08-18 23:44:36 +00:00
spd spd/lp5: Add SPD for MT62F2G32D4DS-023 WT:C 2025-06-28 16:24:28 +00:00
src soc/qualcomm/x1p42100: Support to load CPUCP firmware in x1p42100 2025-08-21 07:11:20 +00:00
tests treewide: Assume FMAP_SECTION_FLASH_START = 0 2025-04-18 14:57:05 +00:00
util lint: Warn about using change IDs for merged changes 2025-08-19 20:57:26 +00:00
.checkpatch.conf .checkpatch.conf: Set max line length to 96 2024-12-04 07:36:22 +00:00
.clang-format Treewide: Fix incorrect SPDX license strings 2024-02-18 01:55:57 +00:00
.editorconfig .editorconfig: Add indent style & size of 2 spaces for shell 2023-12-20 22:30:33 +00:00
.gitignore .gitignore: Ignore payloads/libpayload/generated/ 2024-01-11 14:39:52 +00:00
.gitmodules .gitmodules: Ignore changes make by what-jenkins-does 2025-07-17 20:38:35 +00:00
.gitreview .gitreview: Update default branch from master to main 2023-12-23 16:44:31 +00:00
.mailmap
AUTHORS AUTHORS: Update list to 25.03 2025-05-08 22:32:29 +00:00
COPYING
gnat.adc drivers/intel/gma: Allow SPARK function with side effects 2024-03-01 18:46:30 +00:00
MAINTAINERS MAINTAINERS: Add KunYi Chen as maintainer for LattePanda Mu 2025-07-07 11:42:44 +00:00
Makefile Makefile: Add build/3rdparty as an exception for project_filelist.txt 2025-03-28 20:26:12 +00:00
Makefile.mk tree: Replace scan-build by clang-tidy 2025-07-01 01:12:32 +00:00
README.md Documentation: Update internal URL's 2024-01-04 14:22:51 +00:00
toolchain.mk tree: Replace scan-build by clang-tidy 2025-07-01 01:12:32 +00:00

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary firmware (BIOS/UEFI) found in most computers. coreboot performs the required hardware initialization to configure the system, then passes control to a different executable, referred to in coreboot as the payload. Most often, the primary function of the payload is to boot the operating system (OS).

With the separation of hardware initialization and later boot logic, coreboot is perfect for a wide variety of situations. It can be used for specialized applications that run directly in the firmware, running operating systems from flash, loading custom bootloaders, or implementing firmware standards, like PC BIOS services or UEFI. This flexibility allows coreboot systems to include only the features necessary in the target application, reducing the amount of code and flash space required.

Source code

All source code for coreboot is stored in git. It is downloaded with the command:

git clone https://review.coreboot.org/coreboot.git.

Code reviews are done in the project's Gerrit instance.

The code may be browsed via coreboot's Gitiles instance.

The coreboot project also maintains a mirror of the project on github. This is read-only, as coreboot does not accept github pull requests, but allows browsing and downloading the coreboot source.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://doc.coreboot.org/payloads.html for a list of some of coreboot's supported payloads.

Supported Hardware

The coreboot project supports a wide range of architectures, chipsets, devices, and mainboards. While not all of these are documented, you can find some information in the Architecture-specific documentation or the SOC-specific documentation.

For details about the specific mainboard devices that coreboot supports, please consult the Mainboard-specific documentation or the Board Status pages.

Releases

Releases are currently done by coreboot every quarter. The release archives contain the entire coreboot codebase from the time of the release, along with any external submodules. The submodules containing binaries are separated from the general release archives. All of the packages required to build the coreboot toolchains are also kept at coreboot.org in case the websites change, or those specific packages become unavailable in the future.

All releases are available on the coreboot download page.

Please note that the coreboot releases are best considered as snapshots of the codebase, and do not currently guarantee any sort of extra stability.

Build Requirements and building coreboot

The coreboot build, associated utilities and payloads require many additional tools and packages to build. The actual coreboot binary is typically built using a coreboot-controlled toolchain to provide reproducibility across various platforms. It is also possible, though not recommended, to make it directly with your system toolchain. Operating systems and distributions come with an unknown variety of system tools and utilities installed. Because of this, it isn't reasonable to list all the required packages to do a build, but the documentation lists the requirements for a few different Linux distributions.

To see the list of tools and libraries, along with a list of instructions to get started building coreboot, go to the Starting from scratch tutorial page.

That same page goes through how to use QEMU to boot the build and see the output.

Website and Mailing List

Further details on the project, as well as links to documentation and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://doc.coreboot.org/community/forums.html

Copyrights and Licenses

Uncopyrightable files

There are many files in the coreboot tree that we feel are not copyrightable due to a lack of creative content.

"In order to qualify for copyright protection in the United States, a work must satisfy the originality requirement, which has two parts. The work must have “at least a modicum” of creativity, and it must be the independent creation of its author."

https://guides.lib.umich.edu/copyrightbasics/copyrightability

Similar terms apply to other locations.

These uncopyrightable files include:

  • Empty files or files with only a comment explaining their existence. These may be required to exist as part of the build process but are not needed for the particular project.
  • Configuration files either in binary or text form. Examples would be files such as .vbt files describing graphics configuration, .apcb files containing configuration parameters for AMD firmware binaries, and spd files as binary .spd or text *spd*.hex representing memory chip configuration.
  • Machine-generated files containing version numbers, dates, hash values or other "non-creative" content.

As non-creative content, these files are in the public domain by default. As such, the coreboot project excludes them from the project's general license even though they may be included in a final binary.

If there are questions or concerns about this policy, please get in touch with the coreboot project via the mailing list.

Copyrights

The copyright on coreboot is owned by quite a large number of individual developers and companies. A list of companies and individuals with known copyright claims is present at the top level of the coreboot source tree in the 'AUTHORS' file. Please check the git history of each of the source files for details.

Licenses

Because of the way coreboot began, using a significant amount of source code from the Linux kernel, it's licensed the same way as the Linux Kernel, with GNU General Public License (GPL) Version 2. Individual files are licensed under various licenses, though all are compatible with GPLv2. The resulting coreboot image is licensed under the GPL, version 2. All source files should have an SPDX license identifier at the top for clarification.

Files under coreboot/Documentation/ are licensed under CC-BY 4.0 terms. As an exception, files under Documentation/ with a history older than 2017-05-24 might be under different licenses.

Files in the coreboot/src/commonlib/bsd directory are all licensed with the BSD-3-clause license. Many are also dual-licensed GPL-2.0-only or GPL-2.0-or-later. These files are intended to be shared with libpayload or other BSD licensed projects.

The libpayload project contained in coreboot/payloads/libpayload may be licensed as BSD or GPL, depending on the code pulled in during the build process. All GPL source code should be excluded unless the Kconfig option to include it is set.

The Software Freedom Conservancy

Since 2017, coreboot has been a member of The Software Freedom Conservancy, a nonprofit organization devoted to ethical technology and driving initiatives to make technology more inclusive. The conservancy acts as coreboot's fiscal sponsor and legal advisor.