According to Intel's recommendation for Time Coordinated Computing (TCC)
the FSP-S parameter PchLegacyIoLowLatency should be set to 'Enabled'
in order to promote low latencies on the PCH.
With the previous setting 'Disabled' low latencies on the PCH for
I/O operations are not enhanced.
Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86068
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On x86_32 the xHCI BAR isn't reachable as it's mapped in high MMIO.
Currently this is not a problem since the code is unused.
Add a check and return NULL instead of cutting of the higher bits
and thus do not return an invalid pointer. On x86_64 it's working
when the extended page-tables are installed.
Change-Id: I00496ad476c33e0984d7cb0019f27154302edda5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
On Xeon Skylake-SP with dual sockets the platforms make use of 46bit of
the address space. Most of the PCI BARs reside in high MMIO, not
reachable by x86_32 coreboot.
Add support for x86_64 coreboot and confirm that all supported boards
are booting without errors. This is done by:
- converting all occurrences of VOID * to UINT32 to make sure that
FSP UPDs do not change when pointers are 8byte wide.
- Drop SetupStructPtr as it's unused within FSP and coreboot
TEST: Booted on ocp/tiogapass to Linux. No errors were observed.
Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This patch adds device id for Crashlog and Telemetry. CPU crashlog
record is stored in punit SRAM.
Source: EDS 815002
BUG=None
TEST=Build fatcat and boot with Panther Lake SoC with added
device id.
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Change-Id: I2959623986108a2c5e3dce16e892913a42d71755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change the maximum C state allowed when S0ix isn't used to C8
from C7S to solve the following error:
MWAIT C-state 0x33 not supported by HW (0x1010)
This is a result of copy-pasta from older SOCs, as C7 is not
supported on Alder Lake.
Tested on `starbook_adl` with Ubuntu 24.04 by booting, and
performing multiple S3 cycles.
Change-Id: Idb3e4d34361c8ac25ef144c0d1cda9f801ed0c54
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84622
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The if statement is repeated so merge it into one block.
Change-Id: I92f6d1b0a7fed4730f11e572b076f5dfdb91d96f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Since commit 64d9e85681
("cpu/x86/smm_module_hander: Set up a save state map"), the
smm_get_save_state() function can return a NULL pointer. Therefore, it
is crucial to ensure that code properly handles the potential for a
NULL pointer return value from smm_get_save_state().
Change-Id: Ie263393ca7d9d6b5e9868c5f73240fc788116cd0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The CLFR method exists outside the CNVi device, so add `^` to allow
it to be found. This fixes the SSDT and allows the method to be used.
TEST=build/boot starlabs/starlite_adl
Change-Id: I1158cf1ccf50d9095fdab8d2d663041ef1985513
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit introduces the missing PCI device IDs for Panther Lake
CNVi Bluetooth devices. These IDs are listed in document #815002 -
Panther Lake U/H Processor - External Design Specification Volume 1.
TEST=The CNVB device is now present in the ACPI SSDT table when the
cnvi_bluetooth device is enabled.
Change-Id: I45b42b0694d530763d4cd321aefc64141d088e2b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85959
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor the FSP log level control by introducing a helper function
`fsp_set_debug_level()` to set the serial and MRC debug levels.
This change improves code readability and maintainability by separating
the log level setting logic from the main control flow. It also adds a
check to ensure the configured log levels are valid.
Change-Id: I6efd6a0ea006b4013dce1c8849b7dbbd4ea5e1dc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85934
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit streamlines the call to the
soc_read_core_scaling_factors() function. When runtime access to the
core scaling factors is not available, a static fallback is used based
on the CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR and
CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR options.
TEST=Successfully read performance and efficient scaling factors on a
fatcat board.
Change-Id: I62e903bea07f2981dfcbaf61d3b918e7c332afc5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Suggested-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
There's no reason to tell the OS to disable LTR. On UEFI and
on coreboot's GNR LTR is allowed, thus allow it for all Xeon-SP.
There's no SMM (RAS) code that is able to parse AER structures,
thus let the OS always control AER. On coreboot's GNR AER is
also always granted to the OS.
TEST: Run code on ocp/tiogapass and observed dmesg:
The OS now prints:
acpi PNP0A08:04: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability LTR]
Change-Id: I7c4176a4df898cee28f6319c6684763e825d9c46
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85561
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reduce ACPI code size by using the existing \_SB.POSC instead of
duplicating the method in every PCI/CXL host bridge.
TEST: On ocp/tiogapass the OS still gets granted the PCIe capabilities
as previously through _OSC. Reduces DSDT size by 1366 bytes.
On ibm/sbp1 the OS still gets granted the PCIe capabilities
as previously through _OSC.
Change-Id: I2f25ffbde9b83d286c568202fcffb75ffb07286c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85559
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Guard function prototypes to allow the header to be used in ACPI
ASL code. The defines will be used in the next commit.
Change-Id: Id6c361155c914f168577833279b4b7cc317b2eec
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit adds support for reading core scaling factors via the
PCODE mailbox interface.
Starting with Lunar Lake, the scaling factor information is
centralized in the power control unit (PCU) firmware. In order to keep
all firmware in sync, it is recommended to read the scaling factors
from the PCU firmware instead of using hard-coded values.
The following changes were made:
- Updated the Kconfig file to select
SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS option
- Modified the acpi.h header file to export the cpu_perf_eff_type
enumeration for CPU performance/efficiency types.
- Added a new function to the pantherlake systemagent.c file,
soc_read_core_scaling_factors(), which reads the core scaling
factors from the PCODE mailbox interface. The pcode
READ_CORE_SCALING_FACTOR is presented in document 829201 Panther
Lake Processor Mailbox Command.
The performance impact on boot time is minimal. It took 12 us to read
the scaling factors on a fatcat device.
TEST=Successfully read performance and efficient scaling factors on a
fatcat board.
Change-Id: I7a8e1e66a02e4bf6b1a41277e83c6dec786fe169
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85554
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Starting with Lunar Lake, the scaling factor information is
centralized in the power control unit (PCU) firmware. In order to keep
all firmware in sync, it is recommended to read the scaling factors
from the PCU firmware instead of using hard-coded values.
This commit adds a new Kconfig option,
CONFIG_SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS, to allow
SoC specific code to specify its own function to read the core scaling
factors.
When this option is enabled, the soc_read_core_scaling_factors()
function from the SoC specific code is used to read the core scaling
factors instead of using the statically defined values
CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR and
CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR.
Change-Id: Icdf47e17cc5a6d042f3c5f90cf811fccd6c1ed9b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85553
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disabling RAPL via Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS does
not turn off RAPL completely (i.d. MMIO & MSR).
In the past it was assumed disabling RAPL via MCHBAR is sufficient and
the corresponding changes are also reflected in the related
MSR (0x610-PACKAGE_POWER_LIMIT). This is not the case for
Power Limit 2 (PL2) because Bit[47]-PKG_PWR_LIM_2_EN is still set
although PL1 and PL2 were disabled through MCHBAR.
Thus Bit[10]-POWER_LIMITATION_STATUS flag can be set in
MSR 0x19C (THERM_STATUS) when the power limit of the SKU exceeds.
This may lead to a throttling of the domain level frequency.
Moreover related parameters within the same
MSR (0x610-PACKAGE_POWER_LIMIT) like PKG_PWR_LIM_TIME, PKG_CLMP_LIM,
PKG_PWR_LIM have to be cleared as well for both Power Limits
(PL1 & PL2). This is due to the fact that these parameters stray in to
the system and may effect different system settings.
With this commit the PACKAGE_POWER_LIMIT MSR is cleared additionally to
the MCHBAR setting when build for ElkhartLake.
TEST=Verify MSR(0x610-PACKAGE_POWER_LIMIT) is set to zero during OS
runtime except Bit[15]-PKG_PWR_LIM_1_EN (it is known as a bug that this
bit will be set to 1 anyway).
Moreover using a system stress test tool (e.g. Passmark's BurnInTest)
and stressing the system hard should not lead to
Bit[10]-POWER_LIMITATION_STATUS flag being set. This is the case when
MSR (0x610-PACKAGE_POWER_LIMIT) is not cleared completely and the
system is stressed intensively.
Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85606
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fsp_params.c file is refactored to move the debug message
control logic to a separate function, fsp_control_log_level().
This function takes an FSPM_UPD pointer and a boolean value
indicating whether debug messages should be enabled or disabled.
The fill_fsp_event_handler() function is updated to call
fsp_control_log_level() with the appropriate boolean value based on
the CONFIG(CONSOLE_SERIAL) and CONFIG(FSP_ENABLE_SERIAL_DEBUG)
Kconfig options.
BUG=b:227151510
TEST=Able to build and boot google/fatcat.
Change-Id: Ie2916ce82133058464d20eed327de7c7288e78a4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85827
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This isn't used anywhere, so remove it.
Change-Id: Ieb5980929ef35ae129f9e548da7ab71efa2ae7f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84594
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ASPM helper functions are the same for all Intel SOCs
since Skylake, so move them to common code.
Change-Id: Ic6876e920d75abbbbb27d4ce3a4f2c08a8db9410
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83679
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on discussions on various patches (CB:57140), the idea was to
enable all bits to avoid incomplete ports.
Therefore, enable all bits - the same as ADL.
Change-Id: I5ace878faa09b959384338efcdbdfce390145002
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Document #815002 Panther Lake H Processor - 2.3 Device IDs - Table 8
"Other Device ID" specifies that the first Thunderbolt PCIe root port
number is 21.
The previous offset of 0x10, inherited from Meteor Lake code, caused
an issue that resulted in:
- Temporary deactivation of Thunderbolt PCI devices during ramstage
- Failure to generate critical ACPI SSDT power management data for the
port
This error led to instability in PCIe tunneling during power state
transitions.
Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85781
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the helper functions added to Alder Lake which will configure
ASPM and L1 Subsstate control based on Kconfig, but retain the
capability to override the specific levels from devicetree.
Change-Id: Ia5cc11188b245a93c303117589bd9d3c18c2877e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83678
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix regression introduced in commit 177bb5e9b9
("soc/intel/xeon_sp: Revise IIO domain ACPI name encoding").
Ensure domain ACPI names in the DSDT are in sync with SSDT ACPI names.
Fixes PCI devices not discovered on socket 1-3.
TEST: Booted in ibm/sbp1 and found all PCI devices working, no errors
in dmesg are shown.
Change-Id: Ice168bdebc46dc0cfb9c63c78c46a5d9ff2b7658
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This patch enhances the readability of the CSE sync event
ELOG_TYPE_FW_CSE_SYNC by updating the event naming from "early and late
bootstage" to "pre and post memory."
BUG=b:379585294
TEST=boot verified on google/rex0 and google/rex64
without change:
```
rex-rev3 ~ # elogtool list
rex64-rev3 ~ # /media/usb/elogtool list
3 | 2024-01-01 22:25:59-0800 | Firmware CSE sync | Late CSE Sync
```
with change:
```
rex64-rev3 ~ # elogtool list
3 | 2024-12-17 02:22:36-0800 | Firmware CSE sync | Post RAM CSE Sync
```
Change-Id: Ia5db3ffb43b2ceac821de72ef9e88ed62e617d41
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Rename GSPI2 to GSPI0A to align with the latest Intel documentation
and platform specifications (doc: 815002)
BUG=b:377595986
TEST=Able to see 0x12.6 device is visible using `lspci`.
Change-Id: I9b87d38e44c07a053104b53df38ee1ce14a86c7f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
This change adds the ACPI name "SPI2" for the GSPI2 device
in the Panther Lake SOC.
Replace space with tab for PCI_DEVFN_GSPI2 macro.
w/o this patch:
[ERROR] Missing ACPI Name for PCI: 00:12.6
[ERROR] Missing ACPI Name for PCI: 00:12.6
w/ this patch:
No error
Change-Id: I404ddb893b82836e06d0f52a6d6f2aff2273d8c6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85712
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CSE Sync Early Sign of Life (ESOL) event is logged as soon as the CSE FW
update is complete. This happens irrespective of whether Early Sign of
Life screen is enabled or not. Move CSE Sync ESOL event right before
displaying the ESOL screen.
BUG=b:378458829, b:379585294
TEST=Build Brox BIOS image and boot to OS. Ensure that the ESOL event
for CSE Sync is logged.
Change-Id: Iaa0dbb87ddde69dc3f4a9e058fc6bed8711b29e7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85111
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds an ACPI method to get the LPC Generic Memory Range
(LGMR) address. This is necessary for platforms that need to access
the LGMR from OS driver.
The new method, called GLGM, reads the LGMR address from the LPC PCI
configuration space (offset 0x98) and returns it as a 32-bit value.
BUG=b:354066052
TEST=Able to build and boot google/brox.
Change-Id: I4322cee2c608e550e233c45c68958e8a4046c361
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85602
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make use of exception handling in every stage. Additionally this
enables breakpoints in all stages, making NULL dereferences and
stack overflows easier to detect.
TEST: Stack canary exceptions are seen in romstage on ibm/sbp1.
Change-Id: I8a9f12b9ae041ce47c14f2ef7f09b029d408260e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85569
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit rewrites the CPU topology initialization code to simplify
it and make it more maintainable.
The previous code used a complex set of if-else statements to
initialize the CPU topology based on the CPUID leaves that were
supported. This has been replaced with a simpler and more readable
function that follows the Intel Software Developer Manual
recommendation by prioritizing CPUID EAX=0x1f over CPUID EAX=0xb if
available.
The new code removes the need for separate functions to handle the
topology initialization for different CPUID leaves. It uses a static
array of bitfield descriptors to store the APIC ID descriptor
information for each level of the CPU topology. This simplifies the
code and makes it easier to add new levels of topology in the future.
The code populates the node ID based on the package ID, eliminating
the need for an extra function call.
Change-Id: Ie9424559f895af69e79c36b919e80af803861148
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85576
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Stop using platform_fsp_memory_init_params_cb() as SoC specific romstage
hook and introduce early_pch_init() to do PCH init in romstage before
FSP-M runs.
Move PCH specific code into early_pch_init and call it from common code.
Change-Id: Id31a2018f5820098e83782b19a1672d2e35bdb83
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85505
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The azalia audio device is usually unused on server platforms.
Add code to hide it since FSP lacks this option and there's no
official bit in the IFD to disable it. The device is disabled
early to:
1. Prevent FSP from seeing the device being present. It could keep
an internal state that the device is working.
2. Prevent FSP-M from trying to detect codecs. This would increase
boot time.
3. Prevent FSP from becoming confused or crash when the device is
suddently missing as disabled by a ramstage PCI driver.
TEST: No HDA PCI device visible on ocp/tiogapass.
Change-Id: I84ac53621b2dcf7baa68f2efb30d0b7e77595c8d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85496
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Route IRQ for on-chip end-points only (e.g. 00:1f.4
i801_smbus)
IRQ routing for devices under root ports needs additional
swizzle per decided by root port configurations, which will
postponed to later till there is actual usage.
2. Route IRQ based on FSP programmed end-point device ID <->
PIRQ mapping.
TESTED=Build and boot on intel/avenuecity CRB
Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The ImguClkOutEn parameters are required in pantherlake, therefore,
avoid disabling the IMGU CLKOUT FSP UPDs.
BUG=b:381044394
TEST=Able to see FSP-M UPDs for google/fatcat where IMGU CLKOUTs are
not disabled with this patch.
Change-Id: Ieb022e6dc0b64106ff30f56cd17f9f219276785f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85588
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables the `DEBUG_STACK_OVERFLOW_BREAKPOINTS` and
`DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES` Kconfig options
for the Pantherlake SOC.
These options are causing false positive stack overflow detections,
leading to unnecessary debugging.
w/o this patch:
stack corruption before for verstage and romstage early.
Failed to create address zero instruction fetch breakpoint
Failed to create stack canary breakpoint
...
...
Stack corruption detected at rip: 0xf983007a
Stack corruption detected at rip: 0xf983007a
Change-Id: I31b99a7b6de221d3ec23f6538c078d0797a6084f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85584
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Add GBTR Method, which gets the state of the RF Kill pin. Unlike
the VGPIO, this can be used for both CNVi and full PCI wireless
cards.
Change-Id: I8d025f63192218399b8d5e60e847853e54a8353c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Move BTRK to \_SB.PCI0 so that the CNVi driver can correctly
access it.
Change-Id: I044b745dce41c9d7a86384b42543ad93485d85ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84990
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When variant_update_cpu_power_limits() programs PL4, it systematically
sets the first entry of the power_limits_config SoC chip data
structure. This approach is problematic because the current SoC SKU
may align with a different data structure entry, introducing
inconsistencies.
This commit introduces the power_limits_index field to the
cpu_tdp_power_limits data structure. This field specifies the specific
power limits entry that should be updated.
All data structures utilized by this function are updated accordingly.
BUG=b:380408956
TEST=Able to retrieve collect 28W power_limit.
Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65
Signed-off-by: Subrata Banik <subratabanik@google.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85244
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move PCU specific code into separate files:
- PCUs registers are now locked by the PCI driver final call
- set_bios_init_completion() is not part of PCU1 driver
- Integrate config_reset_cpl3_csrs() into PCU driver
TEST: Still boots on ocp/tiogapass.
Change-Id: Ib4a58b80a1c9fd766946b17c11c629a9df79c573
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85316
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
FSP only configures the PCH IOAPIC. Let coreboot reconfigure all
IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, and the
IOAPICs on Socket1 start at GSI 72, thus calculate the exact GSI
address for each IOAPIC instead of assume it's a linear address space.
Unselect XEON_SP_HAVE_IIO_IOAPIC to prevent soc_get_ioapic_info()
from advertising wrong GSI addresses.
TEST: Booted on ocp/tiogapass with correct GSI bases asigned
matching the _PRT advertised GSI bases.
Xeon Skylake-SP IOAPIC is the same as used on Intel Xeon E7 v2.
See Document Reference Number: 329595-002
Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85170
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch corrects the calculation of the _ADR value for the Intel UFS
controller in the `soc/ufs.h` header file.
The previous calculation incorrectly included a hardcoded value (0x0007)
in the lower bits of the _ADR. This is not in line with the Panther Lake
EDS specification (doc: 815002)
BUG=b:382243957
TEST=Able to build and boot google/fatcat.
> iasl -d /sys/firmware/acpi/tables/DSDT
Device (UFS)
{
Name (_ADR, 0x00170000) // _ADR: Address
Name (_DDN, "UFS Controller") // _DDN: DOS Device Name
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
Change-Id: I889403e4d33efb5818fec06d773b5aec0a74d0b3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85528
Reviewed-by: Divagar Mohandass <divagar.mohandass@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
