soc/intel/alderlake: Change the maximum C state to C8

Change the maximum C state allowed when S0ix isn't used to C8
from C7S to solve the following error:
    MWAIT C-state 0x33 not supported by HW (0x1010)

This is a result of copy-pasta from older SOCs, as C7 is not
supported on Alder Lake.

Tested on `starbook_adl` with Ubuntu 24.04 by booting, and
performing multiple S3 cycles.

Change-Id: Idb3e4d34361c8ac25ef144c0d1cda9f801ed0c54
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84622
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>

src/soc/intel/alderlake/acpi.c

@@ -104,7 +104,7 @@ static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
 static int cstate_set_non_s0ix[] = {
 	C_STATE_C1,
 	C_STATE_C6_LONG_LAT,
-	C_STATE_C7S_LONG_LAT
+	C_STATE_C8
 };
 
 static int cstate_set_s0ix[] = {