erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/xeon_sp: Allow OS to control LTR and AER

Browse source 
There's no reason to tell the OS to disable LTR. On UEFI and
on coreboot's GNR LTR is allowed, thus allow it for all Xeon-SP.

There's no SMM (RAS) code that is able to parse AER structures,
thus let the OS always control AER. On coreboot's GNR AER is
also always granted to the OS.

TEST: Run code on ocp/tiogapass and observed dmesg:
      The OS now prints:
acpi PNP0A08:04: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability LTR]

Change-Id: I7c4176a4df898cee28f6319c6684763e825d9c46
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85561
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
This commit is contained in:
Patrick Rudolph 2024-12-11 12:12:40 +01:00
commit 90196f530f
3 changed files with 9 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
View file

@ -32,8 +32,10 @@
Method (_OSC, 4, NotSerialized) \
{ \
Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3, \
(PCIE_CAP_STRUCTURE_CONTROL| \
(PCIE_LTR_CONTROL| \
PCIE_CAP_STRUCTURE_CONTROL| \
PCIE_PME_CONTROL| \
PCIE_AER_CONTROL| \
PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0)) \
} \
}

4
src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
View file

@ -39,8 +39,10 @@ Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET_NAME, STACK))
Method (_OSC, 4, NotSerialized)
{
Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3,
(PCIE_CAP_STRUCTURE_CONTROL|
(PCIE_LTR_CONTROL|
PCIE_CAP_STRUCTURE_CONTROL|
PCIE_PME_CONTROL|
PCIE_AER_CONTROL|
PCIE_NATIVE_HOTPLUG_CONTROL), 1,
CXL_ERROR_REPORTING_CONTROL))
}

4
src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
View file

@ -37,8 +37,10 @@ Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET_NAME, STACK))
Method (_OSC, 4, NotSerialized)
{
Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3,
(PCIE_CAP_STRUCTURE_CONTROL|
(PCIE_LTR_CONTROL|
PCIE_CAP_STRUCTURE_CONTROL|
PCIE_PME_CONTROL|
PCIE_AER_CONTROL|
PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0))
}
}