soc/intel/xeon_sp/skx: Enable x86_64
On Xeon Skylake-SP with dual sockets the platforms make use of 46bit of the address space. Most of the PCI BARs reside in high MMIO, not reachable by x86_32 coreboot. Add support for x86_64 coreboot and confirm that all supported boards are booting without errors. This is done by: - converting all occurrences of VOID * to UINT32 to make sure that FSP UPDs do not change when pointers are 8byte wide. - Drop SetupStructPtr as it's unused within FSP and coreboot TEST: Booted on ocp/tiogapass to Linux. No errors were observed. Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This commit is contained in:
Patrick Rudolph
Matt DeVillier
parent
ee9adf6d4c
commit
f13b4ca285
3 changed files with 36 additions and 33 deletions
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@ -20,6 +20,9 @@ static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)];
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static void oem_update_iio(FSPM_UPD *mupd)
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{
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UPD_IIO_BIFURCATION_DATA_ENTRY *entry =
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(void *)(uintptr_t)mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTablePtr;
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/* Read GPIO to decide IIO bifurcation at run-time. */
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int slot_config0 = gpio_get(GPP_C15);
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int slot_config1 = gpio_get(GPP_C16);
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@ -28,25 +31,24 @@ static void oem_update_iio(FSPM_UPD *mupd)
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reading the GPIO expander PCA9555 via SMBUS, and then configure the bifurcation
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accordingly is left for future work. */
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if (!slot_config0 && slot_config1)
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mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable[Skt0_Iou0].Bifurcation
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= IIO_BIFURCATE_xxx8xxx8;
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entry[Skt0_Iou0].Bifurcation = IIO_BIFURCATE_xxx8xxx8;
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}
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static void mainboard_config_iio(FSPM_UPD *mupd)
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{
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memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table));
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mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable =
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(UPD_IIO_BIFURCATION_DATA_ENTRY *)iio_table_buf;
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mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTablePtr =
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(uintptr_t)(UPD_IIO_BIFURCATION_DATA_ENTRY *)iio_table_buf;
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mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries =
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ARRAY_SIZE(tp_iio_bifur_table);
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mupd->FspmConfig.IioPciConfig.ConfigurationTable =
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(UPD_PCI_PORT_CONFIG *)tp_iio_pci_port_skt0;
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mupd->FspmConfig.IioPciConfig.ConfigurationTablePtr =
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(uintptr_t)(UPD_PCI_PORT_CONFIG *)tp_iio_pci_port_skt0;
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mupd->FspmConfig.IioPciConfig.NumberOfEntries =
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ARRAY_SIZE(tp_iio_pci_port_skt0);
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mupd->FspmConfig.PchPciConfig.PciPortConfig =
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(UPD_PCH_PCIE_PORT *)tp_pch_pci_port_skt0;
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mupd->FspmConfig.PchPciConfig.PciPortConfigPtr =
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(uintptr_t)(UPD_PCH_PCIE_PORT *)tp_pch_pci_port_skt0;
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mupd->FspmConfig.PchPciConfig.NumberOfEntries =
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ARRAY_SIZE(tp_pch_pci_port_skt0);
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@ -88,7 +90,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
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mainboard_config_iio(mupd);
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/* do not configure GPIO controller inside FSP-M */
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mupd->FspmConfig.GpioConfig.GpioTable = NULL;
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mupd->FspmConfig.GpioConfig.GpioTablePtr = 0;
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mupd->FspmConfig.GpioConfig.NumberOfEntries = 0;
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}
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@ -6,6 +6,8 @@ config SOC_INTEL_SKYLAKE_SP
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select PLATFORM_USES_FSP2_0
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select NO_FSP_TEMP_RAM_EXIT
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select UDK_202005_BINDING
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select HAVE_X86_64_SUPPORT
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select USE_X86_64_SUPPORT
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help
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Intel Skylake-SP support
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@ -37,6 +37,9 @@ are permitted provided that the following conditions are met:
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#pragma pack(1)
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/* Must not use VOID * since that would break x86_64 coreboot support! */
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#define PTR_32B(type) UINT32
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/**
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FSP Header Version Number
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**/
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@ -261,7 +264,7 @@ typedef struct {
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/**
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GPIOTABLE_CONFIG:
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GpioTable - Base Address of the Gpio Table declared by the
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bootloader.
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bootloader. Pointer to UPD_GPIO_INIT_CONFIG.
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Default: NULL
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NumberofEntries - Number of Entries in the GPIO Table provided
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Default: 0
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@ -269,8 +272,8 @@ typedef struct {
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configuration using default GPIO_INIT_CONFIG tables
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**/
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typedef struct {
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UPD_GPIO_INIT_CONFIG *GpioTable;
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UINT32 NumberOfEntries;
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PTR_32B(UPD_GPIO_INIT_CONFIG) GpioTablePtr;
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UINT32 NumberOfEntries;
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} GPIOTABLE_CONFIG;
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/**
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@ -293,7 +296,7 @@ typedef struct {
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/**
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IIOBIFURCATION_CONFIG:
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IIoBifurcationTable - Base Address of the IIO Bifurcation table
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declared by the bootloader
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declared by the bootloader. Pointer to UPD_IIO_BIFURCATION_DATA_ENTRY.
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Default: NULL
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NumberofEntries - Number of Entries in the IIO Bifurcation Table
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Default: 0
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@ -301,8 +304,8 @@ typedef struct {
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bifurcation using default IIO_BIFURCATION_DATA_ENTRY tables
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**/
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typedef struct {
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UPD_IIO_BIFURCATION_DATA_ENTRY *IIoBifurcationTable;
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UINT32 NumberOfEntries;
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PTR_32B(UPD_IIO_BIFURCATION_DATA_ENTRY) IIoBifurcationTablePtr;
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UINT32 NumberOfEntries;
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} IIOBIFURCATION_CONFIG;
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/**
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@ -381,13 +384,12 @@ typedef struct {
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/**
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PCIEPORT_CONFIG:
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PciePortConfiguration - Pointer to an array of PCIe port configuration structures
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as declared above
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as declared above. Pointer to UPD_PCI_PORT_CONFIG.
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NumberOfEntries - Number of elements in the PciePortConfiguration Array
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**/
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typedef struct {
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UPD_PCI_PORT_CONFIG *ConfigurationTable;
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UINT16 NumberOfEntries;
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PTR_32B(UPD_PCI_PORT_CONFIG) ConfigurationTablePtr;
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UINT16 NumberOfEntries;
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} IIOPCIPORT_CONFIG;
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/**
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@ -412,12 +414,13 @@ typedef struct {
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/**
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IIORESOURCE_CONFIG:
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ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array
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ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array.
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Pointer to UPD_IIO_STACK_RESOURCE_CONFIG.
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NumberOfEntries - Number of Entries in the Iio Stack Resource Configuration Array
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**/
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typedef struct {
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UPD_IIO_STACK_RESOURCE_CONFIG *ResourceTable;
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UINT16 NumberOfEntries;
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PTR_32B(UPD_IIO_STACK_RESOURCE_CONFIG) ResourceTablePtr;
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UINT16 NumberOfEntries;
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} IIORESOURCE_CONFIG;
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/**
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@ -436,6 +439,7 @@ typedef struct {
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/**
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PCHPCIPORT_CONFIG:
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PciPortConfig - Pointer to an array of PCH PCI Ports to be configured
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Pointer to UPD_PCH_PCIE_PORT.
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RootPortFunctionSwapping - Disable root port swapping based on device
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connection status
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PciePllSsc - Specifies the Pcie Pll Spread Spectrum Percentage
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@ -446,10 +450,10 @@ typedef struct {
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NumberOfEntries - Number of entries in the PCH PCI Port configuration
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**/
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typedef struct {
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UPD_PCH_PCIE_PORT *PciPortConfig;
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UINT8 RootPortFunctionSwapping;
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UINT8 PciePllSsc;
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UINT16 NumberOfEntries;
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PTR_32B(UPD_PCH_PCIE_PORT) PciPortConfigPtr;
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UINT8 RootPortFunctionSwapping;
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UINT8 PciePllSsc;
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UINT16 NumberOfEntries;
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} PCHPCIPORT_CONFIG;
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/** FSP-M Configuration
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@ -507,12 +511,7 @@ typedef struct {
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**/
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UINT8 BoardId;
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UINT8 reserved2[24];
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/** Offset 0x00C2 **/
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VOID *SetupStructPtr;
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UINT8 reserved3[20];
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UINT8 reserved2[48];
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/** Offset 0x00DA - IioPciConfig
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IIO Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero.
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@ -529,7 +528,7 @@ typedef struct {
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**/
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IIORESOURCE_CONFIG IioResourceConfig;
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UINT8 reserved4[3];
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UINT8 reserved3[3];
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/** Offset 0x00F1 - DCI Enable
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Enable / Disable DCI
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