The calling convention of payload entry function is different by architecture.
For example, X86 takes no arguments and ARM needs first param to be a
cb_header_ptr*.
To help payloads load and execute other payloads easily and correctly, we should
provide the selfboot() function in libpayload, using same prototype as defined
in Coreboot environment.
BUG=none
TEST=emerge-nyan libpayload # pass
BRANCH=none
Change-Id: I8f1cb2c0df788794b2f6f7f5500a3910328a4f84
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199503
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
The libpayload build environment has been changed slightly and here are the
minimal changes to compile ubootcli under ebuild system:
- Allow overriding LIBPAYLOAD_DIR.
- Include only single libpayload.a.
- Revise build flags.
- Increase heap/stack size so video console init is fine.
- Remove abort() which may be defined in libpayload.
- Change weak link default function to non-inline (so it will be provided).
BUG=none
TEST=With a crafted ubootcli.ebuild:
emerge-nyan ubootcli # arm pass
emerge-rambi ubootcli # x86 pass
Change-Id: Icd3bd9f29a3682cd1a2c148a2a57ce44efe33664
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199476
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some EABI conformant toolchains like GCC need additional functions like raise.
To prevent payloads adding arch-specific implementations everywhere, we should
provide the default version in libpayload.
BUG=none
TEST=emerge-nyan libpayload # pass
BRANCH=none
Change-Id: Id1e3c29590aa5881aefd944a7551949ce9a47b8f
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199686
Hook the soc/intel/broadwell directory into the configuration
and build system so it can be used by mainboards.
BUG=chrome-os-partner:28234
TEST=build and boot on wtm2
Change-Id: Ia48ac644a8cefb2cf9c64efaa1bd9737ddfb8b1f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This provides a driver for the ADSP (aka SST -- smart sound tech)
that is built into the southbridge in haswell/broadwell.
This block shares pins with HDA so they cannot both be enabled at
the same time so if HDA is disabled the pins are routed to the
ADSP block.
The ADSP device needs to be put into ACPI mode so a new block of
BARs and enable status is added to the device_nvs structure.
The ACPI _HID is expected to be different for haswell and broadwell
so a new ACPI method is added to check if the PCH is WildcatPoint
and then used in the base ADSP ACPI device definition.
BUG=chrome-os-partner:28234
TEST=Build and boot on samus with ADSP device enabled and check
firmware log for HDA disabled message and that the HDA PCI device
is gone. With sio_acpi_mode=1 the ADSP PCI device is also gone
and is instead enumerated by ACPI.
Change-Id: I73d950725ce29d44a5da9aab00c7f784ba63f2d1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199892
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add defines for PCI device+function for SA/PCH devices and
complete the list by adding entries for devices that were missing.
Then make use of these defines in pch.c and serialio.c.
BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2
Change-Id: Id1b284cfab8a72acf040ea1ce1c38324abccc110
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199891
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The two UARTs built into the haswell/broadwell PCH can be used for
standard console output if configured properly. There is a magic bit
in the IOBP settings for the UART device that will put it into "byte
addressing mode" so it is compatible with standard 16550 UART drivers.
When in this mode the linux kernel driver will be unable to talk to
the device so it is indicated as disabled via the ACPI driver.
Note that this by itself is not enough to get working MMIO UART
in coreboot because the current code is heavily tied with the oxpcie
driver. I have a separate set of patches to disentangle the generic
MMIO UART code from the oxpcie driver but I want to get that series
in upstream first.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I9e689456aa5017784328d1be33ad072f79db1920
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199807
This function will enable the EHCI port 1 on haswell/broadwell
PCH to act as USB debug port. This is hardcoded to port 1.
The EHCI controller must be kept enabled if CONFIG_USBDEBUG
is enabled so this logic is added to the ehci ramstage driver.
BUG=chrome-os-partner:28234
TEST=enable CONFIG_USBDEBUG and build+boot with USB debug output.
Note that libpayload does not support usbdebug yet (I have separate
patches for that) so no payload output is visible.
Change-Id: I704a4786438173b2f3ee2c246636f5a24d8b428c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199412
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CBMEM IDs are converted to symbolic names by both target and host
code. Keep the conversion table in one place to avoid getting out of
sync.
BUG=none
TEST=manual
. the new firmware still displays proper CBMEM table entry descriptions:
coreboot table: 276 bytes.
CBMEM ROOT 0. 5ffff000 00001000
COREBOOT 1. 5fffd000 00002000
. running make in util/cbmem still succeeds
Change-Id: I0bd9d288f9e6432b531cea2ae011a6935a228c7a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199791
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The main benefit of adding this skeleton is the addition of the
correct memory map to CBMEM. Attempts to load depthcharge do not fail
because of unavailability of the bounce buffer.
BUG=chrome-os-partner:27784
TEST=boot updated firmware on AP148, observe
CPU: Qualcomm 8064
in the ramstage console output as well as not failing to load
depthcharge any more.
Change-Id: I56c1fa34ce3967852be6eaa0de6e823e64c3ede8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199675
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Dynamic cbmem support has been enabled on storm, but the proper
initialization at romstage is missing.
Proper DRAM base address definition is also necessary so that CBMEM is
placed in the correct address range (presently at the top of DRAM).
BUG=chrome-os-partner:27784
TEST=build boot coreboot on ap148, observe the following in the
console output:
Wrote coreboot table at: 5fffd000, 0xe8 bytes, checksum 44a5
coreboot table: 256 bytes.
CBMEM ROOT 0. 5ffff000 00001000
COREBOOT 1. 5fffd000 00002000
Change-Id: I74ccd252ddfdeaa0a5bcc929be72be174f310730
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199674
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Include the required modules in romstage and enable early console.
BUG=chrome-os-partner:27784
TEST=observe the romstage prompt in the console output:
coreboot-4.0 romstage Tue May 13 17:08:58 PDT 2014 starting...
Change-Id: Ie3853b9afc53246e6eb997f279ccd4dbb08f748b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199673
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Eliminate duplicated printout and if needed, print only changed
information.
BUG=none
TEST=verified that the 'New segment dstaddr...' message is not
duplicated anymore
Change-Id: Ia13593394fccbb225f2bd9ab2b9228bac29d50fb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is just a convenience - when printing a pre-ram coreboot banner,
add the actual stage name to it.
BUG=none
TEST=manual
. with CONFIG_EARLY_CONSOLE enabled the banners look as follows (the
last one is for ramstage reads 'booting' instead of 'starting'):
coreboot-4.0 bootblock Tue May 13 14:13:37 PDT 2014 starting...
coreboot-4.0 romstage Tue May 13 14:13:37 PDT 2014 starting...
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 booting...
Change-Id: I218c0d3bbfa4a9bdff5632855c520af8626d6495
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199671
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is a placeholder for a real libpayload config, it is fairly close
to the real one and will allow building chrome os image for storm in
the meanwhile.
BUG=chrome-os-partner:27784
TEST=manual
. with this and some other patches 'emerge-storm libpayload
depthcharge' does not fail anymore.
Change-Id: Ie1a96310a7b329fac9d869cfe83005ea20c7e235
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198928
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Fix pointer related casts since this can create a problem for 64-bit systems.
BUG=None
BRANCH=None
TEST=Compiled successfully for link, nyan using emerge-* libpayload
Change-Id: I4cbd2d9f1efaaac87c3eba69204337fd6893ed66
Reviewed-on: https://chromium-review.googlesource.com/199564
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
This adds the Kconfig entries for supporting the broadwell SOC.
This is merged from the various cpu/northbridge/southbridge Kconfig
files that existed for haswell and lynxpoint.
BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2+broadwell
Change-Id: I485b5b80389d5e743e4f8f4c187deb0671a0a697
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199411
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Add a function to initialize the common parts of global NVS.
- Add a function to create the HPET table.
- Add a function to create MADT table overrides.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I304767edf9d5b6ad6059e1015bfca7480723be51
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199409
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Fix header includes
- Use ACPI_BASE_ADDRESS instead of get_pmbase()
- Remove chip_operations as those are now in chip.c
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I28712275a46b64941796bca46ec1bd648b8178f6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199408
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of using a C-state table provided by the mainboard
devicetree use a different set of C-states for S0ix and non-S0ix
systems and use a devicetree setting to choose the appropriate set.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I11175d36fcb68ecad2420e5059234ae1910156f7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199407
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is common code that can be shared across all broadwell
systems instead of being implemented in every main board.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I2535f4d71c28b5804c65619e7818170f5a277e26
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199406
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is very similar to the handling on baytrail platform.
- This late-stage reference code binary is in RW firmware so it
can be updated.
- The reference code binary is in ELF format to be relocated and
executed early in ramstage.
- The reference code binary is staged in SMM region so it can be
reused in the resume path.
- PEI data structure is filled in by common broadwell code as well
as mainboard specific code.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I9a47e7dd4dfaeeafd41a63170e259ef77b8df3e2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199404
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- This driver will get called shortly after ramstage is loaded
and will execute the second reference code binary.
- Prepare for S3 resume handling by determining whether this is
a valid resume path.
- Add function to save the ACPI PM1 wake source on resume for
use in ACPI _SWS method.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ic9f8cfc9f4b9c72d3dfb3b1f3f716d266814bc46
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199403
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to not mess up legacy bootloaders do not reserve the
SMM relocation region but instead backup and restore the contents
during CPU init and SMM relocation.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Icc939d454dd8f3a5a6db917a8a96e3800ebdb1bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199402
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change updates the cfg file for Micron/Samsung 2GB,
792MHz DRAM based on the data generated by t124_emc_reg_tool.
BUG=none
BRANCH=blaze
TEST=emerged coreboot, booted successfully into kernel.
Change-Id: I840cdd967c3b38479946a497a91da89bef5a98ad
Signed-off-by: Jerry Wang <jerryw@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/199296
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
If the kernel does not properly handle the TPM and send it a
TPM_SaveState command before suspend then it will not be in
the correct state on resume. In order to easily detect this
case add a new post code for TPM failure and use it in the
vboot resume path.
BUG=chromium:371105
TEST=Build and boot on wtm2.
Change-Id: I412520b521387a8e18ad1c6f5a64b39cdd5c88ec
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199371
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There is a status bit for this event in most intel chipsets that
we can read and report. Start by adding the new event type.
BUG=chrome-os-partner:28234
TEST=build and boot on wtm2
Change-Id: Ib06411e3b87a1d069fb469943dd445bee6c1291f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199370
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Remove ULT specific hooks and apply them to all broadwell and
haswell CPUs that are supported.
- Rename functions to be more generic rather than haswell specific.
- Clean up code and comments.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I658f47fd653fa702a0039def130e4a92bda4600e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199395
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This code was living in the CPU driver code but it is really part
of the ACPI table generation and should live in acpi.c.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I2393129a535d6cbb9d1c4e4949c3a2db143ff365
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199394
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Fix code and comment formatting.
- Use base address and size info from iomap.h
- Remove unnecessary MCHBAR write to 0x5500
- Use MCH_PAIR define for MCHBAR 0x5418
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Id1b30af2e156a78354dcb457f07f6ed457d8a818
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199393
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Convert most of the init to reg_script format.
- Use global io_apic abstraction instead of hardcoded register
reads and writes.
- Clean up code and comment formatting.
- Remove the code that was setting GPIO routing as that is now
done as part of GPIO setup for LP chipset interface.
- Convert use of get_pmbase() to ACPI_BASE_ADDRESS
- Convert use of DEFAULT_RCBA to RCBA_BASE_ADDRESS
- Add workaround for ULX MPHY PG control based on reference code.
- Static clock gating of SATA Ports is moved to SATA ramstage driver.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ic2386cb01d03b64312a9ac4581baf42e9d0cb716
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199392
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Use device macros from pci_devs.h
- Use base addresses from iobase.h
- Clean up some code and comment formatting
- Remove the SMI that would route USB to XHCI since this
is now done by default at boot time.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: If448b28f2c41c4533c449da8cf63f261c38b5939
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199391
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Move all of the finalize steps from cpu/northbridge/southbridge
into this one file and convert it to (largely) use reg_script format.
- Add a BOOT_STATE_INIT_ENTRY to have this function called as the
last step before boot and resume instead of triggering it from SMI.
- Re-initialize the SPI controller after lockdown so it still works.
- Issue IO write to finalize SMM which will tell SMM to re-init SPI
controller driver after lockdown.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I0ef6506954c193ae668b26ed10160ad4852af5e2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199390
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make the broadwell raminit function closely resemble the baytrail
raminit function. The MRC cache related functions have been split
into the common code at soc/intel/common so we can re-use those
functions here. The PEI data structure is set up in pei_data.c
so we do not need to do any additional configuration of the struct
before starting memory training.
BUG=chrome-os-partner:28234
TEST=Successfully execute mrc.bin on whitecap mountain 2 board to
train memory.
Change-Id: Ie1582d61180e9998d8bfe26758b925b0d4a80840
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Convert most of the init code to use reg_script
- Separate haswell and broadwell init, very similar but there
are subtle differences that make it easier to treat the separately.
- Set up CD clock based on specific IGD type. The initial value
can be selected in devicetree config but may be overridden by specific
limitations of the IGD device. This is configured differently on
haswell and broadwell and is not done in reg_script because of the
subtle requirements for detecting the proper clock frequency.
- Panel setup is currently unchanged although it may not be
entirely correct as I am still waiting for working kernel graphics.
- The i915 init code is removed and the VBIOS is used instead until
we can put more resources into native init.
BUG=chrome-os-partner:28234
TEST=Tested working firmware graphics on samus panel as well as
external panel connected via display port.
Change-Id: I3a910f18ae15d02202e51bde104a9c316338712a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199368
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Remove the IDE and SATA (plan) options since they are not supported
by the chipset.
- Remove the LynxPoint-LP specific checks since only LP variant
is supported.
- Add code to static power gate the unused ports.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ic161abb167cc406163b12c643685a6958382c4a9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199367
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Change the ELOG code for broadwell to use the chipset_power_state
structure found in CBMEM to report events.
- Remove the specific handling of non-LP lynxpoint chipset since
only the LP variant is supported.
- Add a BOOT_STATE_INIT_ENTRY for BS_DEV_INIT to log these events
at boot rather than needing to be called separately.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I78954ab2ce0a9524a5f591b7feaf0097d0296a51
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199366
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Convert the pch early chipset init code to reg_script format.
- Remove the generic romstage code from pch_early_init() as this
is now done in romstage_main().
- Use base addresses from broadwell/iomap.h
- Start the HPET counter after enabling it as it is needed by
the memory training reference code.
- Set PCH interrupt routing here instead of in mainboard code.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I66a8b54ec81d5126cf4d59196e0e06ea949286d1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199365
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Move the System Agent initialization code to a reg_script
implementation and call that initscript in systemagent_early_init.
- Remove the function that was setting up graphics registers as
those are taken care of separately on a per-platform basis.
- Remove some workarounds from older chipsets that were touching
undefined registers in MCHBAR.
- Convert the base addresses to use broadwell/iomap.h
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I1235b631c120d55bf613cf2d195c40a5e5647cc2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199364
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a function to fill out the chipset_power_state structure for
use in romstage and determine the chipset previous sleep state.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ic3d06d28071099f9b1d19ced7754f057cedce574
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199363
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This can be used to raise the core frequency to maximum, but
it may not take effect until BIOS_RESET_CPL bit has been set.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I4841025bad4fa4ab61236e3d7f7f3172061ff39f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is a significant change that is hard to break up. The basic
flow of the file comes from baytrail/romstage/romstage.c and was
overlayed on top of the existing haswell romstage_main and fixed
up where necessary.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I119c7033f4d2980f48e34ab413dfe4845491552b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199361
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Use PCH_DEV_LPC instead of special case for SMM code.
- Change RCBA macros to be SPIBAR macros
- Clean up include files
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I7d846e9c1c4627aea08fb09f2e85f86a98ec61a9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199192
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
romstage: Move the smbus enable code into reg_script format and call
the script with the PCH_DEV_SMBUS device.
ramstage: Use appropriate headers.
both: Change use of old SMBUS_IO_BASE to SMBUS_BASE ADDRESS.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Icf8c70810f86fc56d0f595a80b6d70361f6f7cd8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199191
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a function to the romstage SPI code to read and return the
WPSR to determine the software write protect status at boot.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ia68c02317ed1c2149fd9de1f60598b6f101d9686
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199190
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the stack related helper functions to a separate file
at broadwell/romstage/stack.c.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I9a89899c505e5a99615dd0e4b46a3487e04089f2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
