storm: initialize dynamic cbmem properly

Dynamic cbmem support has been enabled on storm, but the proper
initialization at romstage is missing.

Proper DRAM base address definition is also necessary so that CBMEM is
placed in the correct address range (presently at the top of DRAM).

BUG=chrome-os-partner:27784

TEST=build boot coreboot on ap148, observe the following in the
     console output:

  Wrote coreboot table at: 5fffd000, 0xe8 bytes, checksum 44a5
  coreboot table: 256 bytes.
  CBMEM ROOT  0. 5ffff000 00001000
  COREBOOT    1. 5fffd000 00002000

Change-Id: I74ccd252ddfdeaa0a5bcc929be72be174f310730
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199674
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/google/storm/romstage.c

@@ -19,12 +19,14 @@
 
 #include <arch/stages.h>
 #include <cbfs.h>
+#include <cbmem.h>
 #include <console/console.h>
 
 void main(void)
 {
 	void *entry;
 
+	cbmem_initialize_empty();
 	console_init();
 
 	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");

src/soc/qualcomm/ipq806x/Kconfig

@@ -51,21 +51,24 @@ config RAMSTAGE_BASE
 	hex
 	default 0x4060c000
 
+config SYS_SDRAM_BASE
+	hex
+	default 0x40000000
 
 config STACK_TOP
-        hex
-        default 0x40600000
+	hex
+	default 0x40600000
 
 config STACK_BOTTOM
        hex
        default 0x405fc000
 
 config CBFS_CACHE_ADDRESS
-        hex "memory address to put CBFS cache data"
-        default 0x405e6000
+	hex "memory address to put CBFS cache data"
+	default 0x405e6000
 
 config CBFS_CACHE_SIZE
-        hex "size of CBFS cache data"
-        default 0x00016000
+	hex "size of CBFS cache data"
+	default 0x00016000
 
 endif

src/soc/qualcomm/ipq806x/Makefile.inc

@@ -29,6 +29,7 @@ romstage-y += gpio.c
 romstage-$(CONFIG_SPI_FLASH) += spi.c
 romstage-y += timer.c
 romstage-$(CONFIG_CONSOLE_SERIAL_IPQ806X) += uart.c
+romstage-$(CONFIG_DYNAMIC_CBMEM) += cbmem.c
 
 ramstage-y += cbmem.c
 ramstage-y += clock.c