Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: I6c05212eaf004ea74b7fd3fa92cbaa314474b7e9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87503
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: Id9e75020ab359bf94c75ffc1aaaef7af83d4c9c6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87501
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: Id35705304e872395ce88617c83d9edecb03b02a1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87500
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: I2d2f5c1587bd86c8fee634a49e1ec989c2bef783
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87499
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: I8f55bb7b31936c098da64f65b76965a09981ff73
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87498
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Delete the "TODO: Update for Phoenix" comment from files that have
already been updated in the previous chained patches (CB:85631,
CB:85632, CB:85633).
Change-Id: I137dbba5094ae8cbf842b45d6137c5b0528e5413
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85719
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
This commit updates the platform reporting logic to include support
for Wildcat Lake SoC.
Key changes:
- Add Wildcat Lake-specific entries for MCH, PCH, and IGD device
IDs.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: Ia4efb173f3ff9247d50bcfa496ed92b211729a3a
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87515
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces PCI device details specific to the Wildcat
Lake to Panther Lake code with conditional compilation.
Key changes:
- Add Wildcat Lake-specific PCI device definitions and
configurations, including adjustments to device function
numbers and slot assignments.
- Remove following
- PCIe RP : 00:1c.4 to 00:1c.7
: 00:06.2 & 00:06.3
- Change following
- PCIe RP5 : 00:1c.4 to 00:06.0
- PCIe RP6 : 00:1c.5 to 00:06.1
- Following devices are not present in Wildcat Lake, but their
device definitions are retained as they do not impact
functionality.
- IPU : 00.05.0
- TBT2 : 00.07.2
- TBT3 : 00.07.3
- TCSS_XDCI : 00.0d.1
- TCSS_DMA1 : 00.0d.3
- Update Kconfig to conditionally select COMMON_BLOCK_IPU
only when SOC_INTEL_PANTHERLAKE is selected.
- Modify existing code to utilize the guards, ensuring that
Panther Lake-specific devices and configurations are only
included when appropriate.
- Add configuration options for MAX_TBT_ROOT_PORTS, MAX_ROOT_PORTS,
and MAX_PCIE_CLOCK_SRC with Wildcat Lake values.
MAX_TBT_ROOT_PORTS = 2
MAX_ROOT_PORTS = 6
MAX_PCIE_CLOCK_SRC = 6
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I89f9d9f043d3ff04c0c65dc9d92a76566e901da9
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
This patch introduces a new chipset device tree file for Wildcat
Lake SoC.
Key changes:
- Copy the Panther Lake chipset.cb to chipset_wcl.cb and update
it with device information specific to the Wildcat Lake SoC.
1) Remove following devices:
- Ipu - 00:05.0
- Tbt Rp - 00:07.2 & 00:07.3
- Type-C xDCI - 00:0d.1
- Tcss Dma - 00:0d.3
- Pci Rp - 00:1c.4 to 00:1c.7
- 00:06.2 & 00:06.3
- Two TCSS USB ports
2) Remove Panther Lake Power limits config and add placeholder
for WCL config.
- Guard removed TCSS port references in the shared SoC code with
Kconfig.
- Rename Panther Lake chipset device tree to chipset_ptl.cb to
align with the new device tree naming.
- Update Kconfig to select the newly added chipset device tree
file when the Wildcat Lake SoC is in use.
References:
- Wildcat Lake Processor EDS, Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles without any error.
Change-Id: Ieafb9856daaa48e3ecc6fc9068ae2b2d4019ff80
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87490
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If DRIVERS_WIFI_GENERIC is disabled
`wifi_generic_cnvi_ddr_rfim_enabled` can't be found by the linker.
Additionally if there is no WIFI driver the CNVi DDR RFI Mitigation is
redundant.
Add DRIVERS_WIFI_GENERIC check around `CNVi DDR RFI Mitigation`.
TEST=Boot Intel Alder Lake-P RVP with DRIVERS_WIFI_GENERIC=N and
cnvi_wifi disabled
Change-Id: I4f89ef41a730e38e08886828db0d14f1277ccaf0
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
When soft-disabled, boards selecting SOC_INTEL_CSE_LITE_SKU boot up
with a working state of M3_NO_UMA vs NORMAL, so handle this condition.
Without this, when vboot is not used, the board will simply fail to
boot as vboot_recovery_mode does not exist:
[ERROR] cse_lite: CSE does not meet prerequisites
[ERROR] cse_lite: Failed to get CSE boot partition info
[DEBUG] cse: CSE status registers: HFSTS1: 0x80032044,
HFSTS2: 0x32280126 HFSTS3: 0x50
[EMERG] cse: Failed to trigger recovery mode(recovery subcode:6)
This commit addresses the first error (does not meet prerequisites),
which allows CSE sync to continue and boot the RW partition in
the soft-disabled state. It also allows the CSE to properly transition
back into the normal working state (when that option is selected via
CMOS or CFR).
TEST=build/boot google/wyvern, verify able to disable/enable the ME
properly via CFR option.
Change-Id: I46da5ac248e267acee958d66ebbd97d945e722b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87517
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
When soft-disabled, boards which select SOC_INTEL_CSE_LITE_SKU boot
with their working state having a value of M3_NO_UMA (0x4), as
opposed to the "normal" value of M0_NO_UMA (0x5). Add a define for
this value (taken from older ME code in coreboot) and add a function
to check if the CSE is in that state, which will be used in a
subsequent commit.
TEST=tested with rest of patch train
Change-Id: I405987ece00b3849a9fcdf1bfc8b377fd8d010dc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87516
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit refactors the configuration options for Intel
Panther Lake SoC variants to improve clarity and maintainability.
Key changes:
- Introduce a new SOC_INTEL_PANTHERLAKE configuration option to
serve as a base selection for all Panther Lake SoC variants.
- Update SOC_INTEL_PANTHERLAKE_U_H and SOC_INTEL_PANTHERLAKE_H to
select SOC_INTEL_PANTHERLAKE instead of
SOC_INTEL_PANTHERLAKE_BASE.
- Update existing code to utilize the new SOC_INTEL_PANTHERLAKE
guard where Panther Lake variant guards are applied.
BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles without any error.
Change-Id: I656006dab6f08c9a16996ad194fa0b5b751f91aa
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87511
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The original SPMI calibration process is only suitable for pre-MT8189
SoCs. Update the flow to also support MT8189.
BUG=b:379008996
BRANCH=none
TEST=build pass and driver log is normal:
[INFO ] [Pass] dly:1, pol:0, sampl:0x2
[INFO ] [Pass] dly:1, pol:0, sampl:0x2
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I636b3062fc25fc1d7d39e3426602e6434be4c26a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87508
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some of MTK's ICs (such as the MT8189) use two eFuse registers to
record CPU ID information.
Users can use get_cpu_id and get_cpu_segment_id to obtain the SoC
version. For example, the CPU ID of the MT8189H is 0x81890000, and
the CPU segment ID is 0x21.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I535874025cde7f6f975246105e32e165083601e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87509
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The previous commit incorrectly set GPIO register address due to a lack
of checking. This commit fixes the register address to ensure GPIO
function can work well.
BUG=b:379008996
BRANCH=none
TEST=build passed, and check SD card can be identified in depthcharge
firmware-shell: storage init
Man 000002 Snr 1759900928 Product SA02 Revision 9.12
* 0: UFS LUN 0
1: removable mtk_mmc
2 devices total
Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
Change-Id: I14125ff331f965ce8cbb83cb25d8a2feff0359f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87510
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 12abfb43dc ("soc/intel/cnvi: Add CNVW OpRegion") added an
ACPI function call to \_SB_.PCI0.GPCB(), which is present in the SoC
common northbridge.asl, but not in the ApolloLake northbridge.asl.
Add the missing GPCB function to the APL northbridge. Per Intel doc
336561, the PCIEXBAR starts at bit 28 vs 26 on other platforms.
TEST=build/boot google/ampton, verify no ACPI errors in dmesg related
to missing function/object, Windows boots without ACPI_BIOS_ERROR BSOD.
Change-Id: Ib45d655a30bf68e9b3d24a444c505e515c4950a6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87486
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up `Device4Enable` FSP setting to devicetree state and drop its
redundant devicetree setting `Device4Enable`. For boards where the
register setting and PCI device status are not in agreement, use
the register setting to determine the PCI device status, since that
is what FSP uses.
Modeled after similar patches for other SoCs.
Change-Id: If17e6e86f6933b334e13f2c05ca513cef0998996
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87483
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some mainboards use the common DPTF ASL rather than the DPTF chip
driver, and those boards need to skip generation of the TCPU ACPI
device in order to avoid a duplicate being created and causing
issues with ACPI table parsing. Create a Kconfig that affected
boards will select to skip generating the TCPU in the SSDT.
Change-Id: Iec58d480821a273cdb4ff086f4995d21fd4bdb2e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
NUM_COMx_GRP_PADS value is calculated based on COMx_GRP_PAD_END
and COMx_GRP_PAD_START values instead of using GPIO pin names.
TEST=Compiled and Verified on Wildcat Lake Simulation Platform.
Change-Id: I0c5b2ebc00f328bd4b9df4653d5339781e38fcba
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Key changes:
- Relocate the package corresponding to CPUJTAG group from GPI3
device to the GPI4 device in the ACPI table, utilizing a Kconfig
guard for conditional compilation.
- Add ACPI IDs specific to Wildcat Lake GPIO communities.
- Select SOC_INTEL_PANTHERLAKE_BASE for SOC_INTEL_WILDCATLAKE to
clearly differentiate between Panther Lake and Wildcat Lake
changes.
References:
- Wildcat Lake EDS Volume 2 (#829345)
- Wildcat Lake GPIO Implementation Summary (#836031)
BUG=b:394208231
TEST=Both Ocelot and Fatcat variants are built
Change-Id: I934c193c75e459c72cc8b01a575cc0bbd65dc273
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch introduces GPIO changes for the Wildcat Lake SoC.
These changes coexist with the Panther Lake SoC GPIO files.
Key Changes:
- The CPUJTAG group is moved from community 3 to community 4.
- A new pin is added to Group H.
- Wildcat Lake-specific register definitions are included.
- Kconfig is utilized to segregate Wildcat Lake GPIO changes.
References:
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
- Wildcat Lake GPIO Implementation Summary (#836031)
BUG=b:394208231
TEST=Both Ocelot and Fatcat variants are built
Change-Id: Ib364d41097c53cd085c6cf89b0461ce38117b21e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87452
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Sending the disable and EOP commands will not work if flash descriptor
override is set on Meteor Lake.
Change-Id: I3b5a56229434c9cc326141d48359faa7759541ee
Signed-off-by: Jeremy Soller <Jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
This commit updates the pre-allocated IGD stolen memory size for Intel
Panther Lake SoCs from 128MB to 64MB within the FSP-M configuration
parameters.
Reducing the IGD stolen memory allocation from 128MB to 64MB
significantly optimizes system memory resource utilization (by 64MB).
Furthermore, this reduction frees one MTRR. Previously, the 128MB IGD
allocation consumed all 10 available BIOS MTRRs; the new 64MB allocation
now leaves MTRR index 9 available.
BUG=b:413638298
TEST=Able to boot google/fatcat to OS w/ internal and/or external
display attached.
Change-Id: Ifd60973bc5d37cbbc4ea6c8eaf5d851069d53083
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87460
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit refactors the HDA initialization within the common Intel
SoC block to provide mainboard-level customization.
A new weak function, mainboard_is_hda_codec_enabled(), is
introduced. The `hda_init()` function invokes `azalia_audio_init()` when
`CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB)` is enabled and
`mainboard_is_hda_codec_enabled()` is also true.
The default (weak) implementation of `mainboard_is_hda_codec_enabled()`
simply returns `true`, ensuring that the original behavior is maintained
for mainboards that do not provide an override.
This change allows specific mainboards to implement their own
`mainboard_is_hda_codec_enabled()` to specify if hardware design has
support for HDA codec depending upon the firmware config (FW_CONFIG) for
the audio subsystem.
BUG=b:413638298
TEST=Able to build and boot google/fatcat.
Change-Id: Ided1413e828f6bc3421e538a969c38e15b5f3116
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Update the default Kconfig values for the `soc/qualcomm/x1p42100`
to specify the correct hardware instances/buses used for various
peripherals as per datasheet for bluey (dated 04/15).
Changes:
- Boot SPI flash bus set to 24.
- Console UART instance set to 21.
- Select FIXED_UART_FOR_CONSOLE Kconfig as UART is not really
selectable due to GPIO Function 0 (bit-bang mode) default
configuration.
Additionally, remove previous used TODO placeholders.
BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.
Change-Id: Ia053edb731f7e08c98ffa3fe273ddd1c97b651bb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87272
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds QUP-SE entries as applicable for the Qualcomm X1P-42-100
SoC.
This includes:
- Add new entries for QUPV3_2 SEs.
- Update base addresses for all QUP-SEs.
- Base GPIO pin function assignments.
- Definition and GPIO mapping for relevant QUP Serial Engines (SEs).
- GPIO mapping for the QSPI interface.
Additionally, update GPIO PINS for QSPI and UART.
BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.
Change-Id: Ib0535aa5dfadef8c412c5e9dd51859068539821f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
TEST=build/boot google/guado with CFR options enabled.
Change-Id: Iaf9950a3b446b1b55d836e54e8b231d047571768
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87387
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I925002958b5de93e833f06fddf772e5334a7bdb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: Iaddaf56563bd5916bc27d99171af48bf46127052
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87399
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This commit introduces a basic SoC framework for the Qualcomm
X1P-42-100, enabling initial build integration.
Key changes:
- Add placeholder SoC callbacks to facilitate control flow from /lib
and Qualcomm common code.
- Populate the x1p42100 SoC directory with a copy of the SC7280
codebase, with SoC-specific implementations removed.
This provides a foundational structure for X1P-42-100 development
within the `soc/qualcomm/x1p42100` directory, ensuring the upstream
builder can successfully compile the SoC code.
This allows for incremental development and integration.
Reference Document: X1P42100 Hardware Register Description
BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.
Change-Id: I6358177b9c6dc26967d364a2056a62d8ca77f89b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Some SoC like Glinda,
1. It has multiple L3 caches block, each identified by a unique cache
UID. Each core is associated with a specific L3 cache, which can be
determined based on the CPU core ID.
2. Each CPU core have slightly different CPU boost frequency.
For L3 cache info in DMI table type 7, the default implementation
(x86_get_cpu_cache_info) retrieves cache information only for the
current core and assumes that the same L3 cache is shared across all
cores.
To accurately determine the total L3 cache size:
1. Retrieves L3 cache information for each CPU core.
2. Identifies the unique cache ID associated with each core.
3. Aggregates cache sizes for all unique cache IDs to compute the
total L3 cache size, ensuring correct summation even when L3 cache
blocks have different sizes.
Additionally to get core max boost frequency,
1. Determine max boost frequency among all cores & update
smbios_cpu_get_max_speed_mhz such that it return max of all cores.
TEST=Build for Glinda SoC & check output of `dmidecode -t 7` &
`dmidecode -t 4`. Verify DMI Type7 table to report L3 cache size as 24MB
(16 + 8) & Also verify DMI Type4 'Max Speed: 5408 MHz' which is maximum
boost clock frequency.
Change-Id: I2569a9c744f7f41e4df692626e77a178184b7e0e
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
To promote code reuse and maintainability, move i2c functions to common
folder. The function prototype "mtk_i2c_bus_init(uint8_t bus)" used by
some legacy platforms are changed to "mtk_i2c_bus_init(uint8_t bus,
uint32_t speed)" for better API integration.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I6ac7009f5af4e6379d3f73aec61d0f4abd28471c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87352
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The parameter CPU isn't used, thus drop it.
Change-Id: Ie7f6179f0545f905463752e94243b438143d8234
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This patch adds Wildcat Lake-specific CPU and PCIe device IDs to the
header files and driver-specific code.
Reference:
Wildcat Lake Processor Prelim External Device IDs (820363)
BUG=b:394208231
TEST=Verified on Wildcat Lake Simulation Platform
Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87262
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I97d5d8b78cc9e5516dbfc64f81a925b1715b941b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: I1c51e653a9e34bb7f5ac07bcae8481be269f83cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the IGD config options IgdDvmt50PreAlloc and ApertureSize to the
option API, so they can be configured at runtime without recompilation.
The Aperture size falls back to the FSP default value, so no change if
unconfigured.
Change-Id: Idad22ca79c10d575320b4360ec24c2019a837446
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Add an option variable 'me_disable' to control the visibility of the
HECI PCI device at runtime. Default to the Kconfig selection if not set.
Change-Id: I6e7c018115780c74f1662948ed8dad3e0559051a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: Id69295ae1708164b1afbafe5724e19bf13fc3963
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87393
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the IGD config options IgdDvmt50PreAlloc and ApertureSize to the
option API, so they can be configured at runtime without recompilation.
The Aperture size falls back to the FSP default value, so no change if
unconfigured.
Change-Id: Ic900cb7bdc6dc532aef0c0b51b32bf8308a8ae36
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87392
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: I1684439755db9d8194ac5533513e65c9ba8f0768
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I734262c8191bc217c721c0174d0f844755bc73a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79917
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 2fdfa50437.
Reason for revert: libbl31.a is under refactoring. Stop linking to this
library before finalizing the binary. This patch will be re-landed when
the binary is ready.
BUG=b:412560091
Change-Id: Ie2c315141a51f30027414cfe59552cb50f2b52f6
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87414
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
