fb3f025ea6
Some SoC like Glinda, 1. It has multiple L3 caches block, each identified by a unique cache UID. Each core is associated with a specific L3 cache, which can be determined based on the CPU core ID. 2. Each CPU core have slightly different CPU boost frequency. For L3 cache info in DMI table type 7, the default implementation (x86_get_cpu_cache_info) retrieves cache information only for the current core and assumes that the same L3 cache is shared across all cores. To accurately determine the total L3 cache size: 1. Retrieves L3 cache information for each CPU core. 2. Identifies the unique cache ID associated with each core. 3. Aggregates cache sizes for all unique cache IDs to compute the total L3 cache size, ensuring correct summation even when L3 cache blocks have different sizes. Additionally to get core max boost frequency, 1. Determine max boost frequency among all cores & update smbios_cpu_get_max_speed_mhz such that it return max of all cores. TEST=Build for Glinda SoC & check output of `dmidecode -t 7` & `dmidecode -t 4`. Verify DMI Type7 table to report L3 cache size as 24MB (16 + 8) & Also verify DMI Type4 'Max Speed: 5408 MHz' which is maximum boost clock frequency. Change-Id: I2569a9c744f7f41e4df692626e77a178184b7e0e Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> |
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