soc/mediatek/mt8189: Add I2C driver support
Add I2C controller driver. BUG=b:379008996 BRANCH=none TEST=build passed Signed-off-by: ot_ryanw.wang <ot_ryanw.wang@mediatek.com> Change-Id: I4baa291a83ecce60eb2d41e329c2182f3ea273b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
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ot_ryanw.wang
Yidi Lin
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4 changed files with 214 additions and 0 deletions
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@ -4,6 +4,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8189),y)
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all-y += ../common/flash_controller.c
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all-y += ../common/gpio.c ../common/gpio_op.c ../common/gpio_eint_v2.c gpio.c gpio_eint.c
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all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
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all-$(CONFIG_SPI_FLASH) += spi.c
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all-y += ../common/timer_prepare.c timer.c
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all-y += ../common/uart.c
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114
src/soc/mediatek/mt8189/i2c.c
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114
src/soc/mediatek/mt8189/i2c.c
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@ -0,0 +1,114 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/*
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* This file is created based on MT8189 Functional Specification
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* Chapter number: 9.10
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*/
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#include <assert.h>
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#include <console/console.h>
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#include <device/i2c_simple.h>
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#include <device/mmio.h>
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#include <gpio.h>
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#include <soc/i2c.h>
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struct mtk_i2c mtk_i2c_bus_controller[] = {
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[0] = {
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.i2c_regs = (void *)I2C0_BASE,
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.i2c_dma_regs = (void *)I2C0_DMA_BASE,
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[1] = {
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.i2c_regs = (void *)I2C1_BASE,
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.i2c_dma_regs = (void *)I2C1_DMA_BASE,
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[2] = {
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.i2c_regs = (void *)I2C2_BASE,
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.i2c_dma_regs = (void *)I2C2_DMA_BASE,
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[3] = {
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.i2c_regs = (void *)I2C3_BASE,
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.i2c_dma_regs = (void *)I2C3_DMA_BASE,
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[4] = {
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.i2c_regs = (void *)I2C4_BASE,
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.i2c_dma_regs = (void *)I2C4_DMA_BASE,
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[5] = {
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.i2c_regs = (void *)I2C5_BASE,
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.i2c_dma_regs = (void *)I2C5_DMA_BASE,
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[6] = {
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.i2c_regs = (void *)I2C6_BASE,
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.i2c_dma_regs = (void *)I2C6_DMA_BASE,
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[7] = {
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.i2c_regs = (void *)I2C7_BASE,
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.i2c_dma_regs = (void *)I2C7_DMA_BASE,
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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[8] = {
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.i2c_regs = (void *)I2C8_BASE,
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.i2c_dma_regs = (void *)I2C8_DMA_BASE,
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.mt_i2c_flag = I2C_APDMA_ASYNC,
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},
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};
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_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER,
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"Wrong size of mtk_i2c_bus_controller");
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static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = {
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[0] = {
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PAD_FUNC_UP(SCP_SDA0, SDA0),
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PAD_FUNC_UP(SCP_SCL0, SCL0),
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},
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[1] = {
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PAD_FUNC_UP(SCP_SDA1, SDA1),
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PAD_FUNC_UP(SCP_SCL1, SCL1),
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},
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[2] = {
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PAD_FUNC_UP(SDA2, SDA2),
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PAD_FUNC_UP(SCL2, SCL2),
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},
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[3] = {
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PAD_FUNC_UP(SDA3, SDA3),
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PAD_FUNC_UP(SCL3, SCL3),
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},
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[4] = {
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PAD_FUNC_UP(SDA4, SDA4),
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PAD_FUNC_UP(SCL4, SCL4),
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},
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[5] = {
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PAD_FUNC_UP(SDA5, SDA5),
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PAD_FUNC_UP(SCL5, SCL5),
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},
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[6] = {
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PAD_FUNC_UP(SDA6, SDA6),
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PAD_FUNC_UP(SCL6, SCL6),
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},
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[7] = {
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PAD_FUNC_UP(SDA7, SDA7),
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PAD_FUNC_UP(SCL7, SCL7),
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},
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[8] = {
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PAD_FUNC_UP(SDA8, SDA8),
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PAD_FUNC_UP(SCL8, SCL8),
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},
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};
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void mtk_i2c_set_gpio_pinmux(uint8_t bus)
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{
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assert(bus < I2C_BUS_NUMBER);
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const struct pad_func *ptr = i2c_funcs[bus];
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for (size_t i = 0; i < 2; i++) {
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gpio_set_mode(ptr[i].gpio, ptr[i].func);
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gpio_set_pull(ptr[i].gpio, GPIO_PULL_DISABLE, ptr[i].select);
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}
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}
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@ -40,10 +40,28 @@ enum {
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DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0103C000,
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SSUSB_IPPC_BASE = IO_PHYS + 0x01263E00,
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UFSHCI_BASE = IO_PHYS + 0x012B0000,
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I2C0_DMA_BASE = IO_PHYS + 0x01300200,
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I2C1_DMA_BASE = IO_PHYS + 0x01300300,
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I2C2_DMA_BASE = IO_PHYS + 0x01300400,
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I2C3_DMA_BASE = IO_PHYS + 0x01300500,
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I2C4_DMA_BASE = IO_PHYS + 0x01300600,
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I2C5_DMA_BASE = IO_PHYS + 0x01300700,
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I2C6_DMA_BASE = IO_PHYS + 0x01300800,
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I2C7_DMA_BASE = IO_PHYS + 0x01300900,
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I2C8_DMA_BASE = IO_PHYS + 0x01300A00,
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SSUSB_SIF_BASE = IO_PHYS + 0x01B00300,
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I2C2_BASE = IO_PHYS + 0x01B20000,
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MIPITX0_BASE = IO_PHYS + 0x01B40000,
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IOCFG_LM_BASE = IO_PHYS + 0x01B50000,
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EDP_BASE = IO_PHYS + 0x01B70000,
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I2C0_BASE = IO_PHYS + 0x01C20000,
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I2C1_BASE = IO_PHYS + 0x01C21000,
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I2C3_BASE = IO_PHYS + 0x01D70000,
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I2C4_BASE = IO_PHYS + 0x01D71000,
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I2C5_BASE = IO_PHYS + 0x01D72000,
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I2C6_BASE = IO_PHYS + 0x01D73000,
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I2C7_BASE = IO_PHYS + 0x01F30000,
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I2C8_BASE = IO_PHYS + 0x01F31000,
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IOCFG_RB0_BASE = IO_PHYS + 0x01C50000,
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IOCFG_RB1_BASE = IO_PHYS + 0x01C60000,
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IOCFG_BM0_BASE = IO_PHYS + 0x01D20000,
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81
src/soc/mediatek/mt8189/include/soc/i2c.h
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81
src/soc/mediatek/mt8189/include/soc/i2c.h
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@ -0,0 +1,81 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/*
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* This file is created based on MT8189 Functional Specification
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* Chapter number: 9.10
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*/
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#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_I2C_H__
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#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_I2C_H__
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#include <soc/i2c_common.h>
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/* I2C Register */
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struct mt_i2c_regs {
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uint32_t data_port;
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uint32_t reserved0[1];
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uint32_t intr_mask;
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uint32_t intr_stat;
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uint32_t control;
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uint32_t transfer_len;
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uint32_t transac_len;
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uint32_t delay_len;
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uint32_t timing;
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uint32_t start;
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uint32_t ext_conf;
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uint32_t ltiming;
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uint32_t hs;
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uint32_t io_config;
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uint32_t fifo_addr_clr;
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uint32_t reserved1[2];
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uint32_t transfer_aux_len;
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uint32_t clock_div;
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uint32_t time_out;
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uint32_t softreset;
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uint32_t reserved2[16];
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uint32_t slave_addr;
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uint32_t reserved3[19];
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uint32_t debug_stat;
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uint32_t debug_ctrl;
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uint32_t reserved4[2];
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uint32_t fifo_stat;
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uint32_t fifo_thresh;
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uint32_t reserved5[897];
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uint32_t sec_control;
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uint32_t reserved6[31];
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uint32_t channel_lock;
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uint32_t channel_sec;
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uint32_t hw_cg_en;
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uint32_t reserved7[1];
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uint32_t dma_req;
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uint32_t dma_nreq;
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};
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check_member(mt_i2c_regs, intr_mask, 0x08);
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check_member(mt_i2c_regs, transfer_aux_len, 0x44);
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check_member(mt_i2c_regs, slave_addr, 0x94);
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check_member(mt_i2c_regs, debug_stat, 0xE4);
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check_member(mt_i2c_regs, fifo_stat, 0xF4);
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check_member(mt_i2c_regs, sec_control, 0xF00);
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check_member(mt_i2c_regs, channel_lock, 0xF80);
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check_member(mt_i2c_regs, dma_req, 0xF90);
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check_member(mt_i2c_regs, dma_nreq, 0xF94);
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/* I2C ID Number*/
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enum {
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I2C0,
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I2C1,
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I2C2,
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I2C3,
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I2C4,
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I2C5,
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I2C6,
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I2C7,
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I2C8,
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};
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#define I2C_BUS_NUMBER 9
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#define MAX_CLOCK_DIV 32
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#define I2C_CLK_HZ 124800000
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#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_I2C_H__ */
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