Matt DeVillier 1e7e4e943f soc/intel/tigerlake: Hook up S0ix setting to option API ... Hook up the s0ix_enable setting to the option API, so it can be changed at runtime without recompilation. Default to the value set by the mainboard. Change-Id: I6c05212eaf004ea74b7fd3fa92cbaa314474b7e9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87503 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>		2025-05-08 12:27:37 +00:00
..
amd	soc/amd/phoenix: Remove outdated TODO comments	2025-05-07 16:35:47 +00:00
cavium	soc/cavium: Fix non matching types	2024-08-30 07:34:47 +00:00
example/min86
ibm/power9	3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER	2024-09-06 13:55:50 +00:00
intel	soc/intel/tigerlake: Hook up S0ix setting to option API	2025-05-08 12:27:37 +00:00
mediatek	soc/mediatek/common: Update SPMI calibration process	2025-05-03 10:10:25 +00:00
nvidia	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
qualcomm	soc/qualcomm/x1p42100: Set correct Kconfig defaults for peripherals	2025-04-26 03:58:57 +00:00
rockchip	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
samsung	samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'	2025-01-15 08:32:16 +00:00
sifive	tree: Remove unused <assert.h>	2024-11-19 00:40:04 +00:00
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00