Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
AMD SoC from family 17h share common cpu init code.
Move those to common/block/cpu/noncar/cpu.c
TEST=Build for glinda SoC & check for boot.
Change-Id: If53455f359302f368f7c979defa2c1088c5c2f16
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
To allow adding more scripts to the util/mtkheader folder, rename it to
util/mediatek. Also update description.md and regenerate
Documentation/util.md and util/README.md by util_readme.sh.
Change-Id: Ibc6ef9dddc541d2dd471898af431cadde231edca
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
HW TX tracking works by writing a pattern to the designated DRAM buffer
and then reading it back automatically to calculate the appropriate TX
time delay. To avoid writing the pattern to system-used memory, we need
to permanently reserve last 64KB memory on each rank for the HW TX
tracking feature.
BUG=b:379008996
BRANCH=none
TEST=Reserve memory ok
Firmware shows the following log :
000000013fff0000-000000013fffffff: RESERVED
000000023fff0000-000000023fffffff: RESERVED
Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I2ecfe42dc9f1882163d03f50cf9b5ff8e98c2972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
To promote code reuse and maintainability, this commit moves the DRAMC
parameter function declarations to the common folder.
BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Iab24f07b4c02da22779ea1c76f3237c144d92b98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The configuration method of the reserved DRAM buffer used for HW TX
TRACING on MT8196 is also applicable to other SoCs, such as MT8189.
To facilitate reuse, we move the relevant files to the common directory.
BUG=b:379008996
BRANCH=none
TEST=Reserve memory ok
Firmware shows the following log with 12GB DDR board:
00000001ffff0000-00000001ffffffff: RESERVED
000000037fff0000-000000037fffffff: RESERVED
Change-Id: I3fdd9d2f7ab1bbdcc097510556929da2134f7d95
Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Add DRAM calibration support for mt8189. DRAM parameters and related
constants are added in dramc_param.h and dramc_soc.h.
The common emi.c can be reused for MT8189 as well, so remove the
duplicate mt8189/emi.{c,h}.
Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast
calibration via the DRAM blob.
BUG=b:379008996
BRANCH=none
TEST=Boot up pass and see log
3200 LPDDR5 chan0(x16) rank0: memory test pass
3200 LPDDR5 chan0(x16) rank1: memory test pass
3200 LPDDR5 chan1(x16) rank0: memory test pass
3200 LPDDR5 chan1(x16) rank1: memory test pass
Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: Ia6f6e5afc1f4a2e919243bda0799712cd7b4d01f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
FMAP should not contain information about the memory map.
Done with the following command:
"find -name \*.fmd -exec sed -i 's/\(FLASH\).* \(.*\) /\1 \2 /' {} \;"
for AMD:
All addresses that amdfwtool expects as command line parameter have the
ADDR_REL_BIOS (flash address) address_mode setting. One exception is
the *_FW_A_POSITION and *_FW_B_POSITION addresses. But amdfwtool checks
if memory or flash addresses are passed and converts accordingly. So
changing the address from memory -> flash doesn't matter for the
resulting binary.
Since commit 41a162b7a8 ("soc/amd/phoenix/Makefile.inc: Pass APOB_NV
address as offset") and therefore since phoenix SOC, APOB_NV is passed
as flash offset. But before that the memory ABL always assumed a MMIO
address (no matter the address_mode) so we need to add a little quirk
for that.
tested: boot glinda based mainboard and also check that memory training
is still cached successfully in APOB_NV.
Change-Id: Iac86ef9be6b14817a65bf3a7ccb624d205ca3f99
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This patch moves eSOL enablement from the SoC level to the mainboard level. This gives the mainboard the option to not use eSOL if it's not supported.
The FSP_UGOP_EARLY_SIGN_OF_LIFE Kconfig option is now enabled for the Fatcat and Felino boards.
This option was previously enabled at the SoC level for Pantherlake,
but is now being enabled specifically for these mainboards.
BUG=b:400550435
TEST=Build the Fatcat and Felino targets. Verify that the eSOL works
fine.
Change-Id: Ie0cf5b00f75071640475d61420824cb2b89b4103
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87236
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Must have been accidentally happened when copying phoenix to glinda.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I78996cd35085c7649c4952d9b121957c8cedd84b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86865
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The Kconfig options `USE_INTEL_FSP_MP_INIT` and
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` are mutually
exclusive ways for the FSP to handle MP initialization.
This commit updates the `default` condition for
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` to `y if
!USE_INTEL_FSP_MP_INIT`. This ensures that if
`USE_INTEL_FSP_MP_INIT` is enabled,
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` will default
to disabled, preventing potential conflicts in MP initialization.
The explicit `depends on
!USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI`
on `USE_INTEL_FSP_MP_INIT` is no longer strictly necessary due to
this change in the default value, but it is kept for clarity and
to explicitly state the mutual exclusivity.
TEST=Able to choose USE_INTEL_FSP_MP_INIT Kconfig for
google/fatcat.
Change-Id: I9ecc7b50ed6a6b13c4ccde0a49f50a40b606a848
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87161
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
MSR definition in soc/amd/*/include/soc/msr.h are the same & hence move
them to common header src/include/cpu/amd/msr.h
Change-Id: Ic0cb54b13320f8a38e70c0a76d9b9a51ba0ea01d
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87124
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Also remove include folders that don't even exist.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic64f5187e50b903af5461bfa4d57bb4951d3b501
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86864
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Correct XHCI and PHY register addresses and enable USB port 3 VBUS
to support USB host functionality.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Change-Id: I5f1b4b3eb178cb9a110b97a2763c8cff5cdf0ddd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87021
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The double negation (`!!`) was unnecessarily used when assigning the
`pch_hda_sdi_enable` type boolean from the SOC config to the FSP M
config.
This commit removes the redundant `!!` operator, directly assigning
the boolean value of `config->pch_hda_sdi_enable[i]` to
`m_cfg->PchHdaSdiEnable[i]`.
TEST=Able to build and boot google/fatcat.
Change-Id: I9233116ca2bfaeac2f685d464a1cb261f067db6a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87109
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The arch include files are overshadowed by PSP verstage include files.
The reason is that psp_verstage implements its own set of inb() and
outb() functions, which use a runtime configurable IO base address
instead of a built time constant.
But this works at the moment only because of the order in which the
include files are added. Since that is very error prone, this patch
introduces another solution to the problem.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I16fa4a4cb5168024aaef30119e9aa8a34dbaacbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit introduces the necessary changes to configure the Touch
Host Controller User Platform Data (UPD) fields such as ThcAssignment,
ThcMode, and ThcWakeOnTouch according to the specific SoC chip
configuration derived from the devicetree.
Key changes include:
- Creation of override functions to supply SoC-specific configurations
for the Touch Host Controller (THC).
- Addition of a new SoC-specific THC header file.
- Inclusion of a motherboard (MB)-specific THC header file.
- Establishment of a build path to allow devicetree to leverage
variant-specific defines.
BUG=none
TEST=Add CONFIG_DRIVERS_INTEL_TOUCH to fatcat board with the devicetree
changes for touchscreen and/or touchpad, as well as proper CBI settings.
Boot the board to OS and check that the THC SoC-specific info is
generated in the SSDT.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I15fb62eaadc03b9a17e94609b97c686518150e2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85199
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A glinda based platform reports:
[WARN] RAM APOB data is too large (3b3b0 + 8) > 1e000
APOB NV size is not enough on recent platforms to cache memory training,
which causes the same amount of boot time on subsequent boots as on the
first boot.
This time increase the size properly by adjusting the base address of
the components that come after the APOB region.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I070cf766b98825cd5ff37674e1f9651fa71159c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This reverts commit 362232d236.
Reason for revert:
This introduced an overlap between APOB DRAM region and SHAREDMEM
region used for PSP verstage. Our linker scripts would have caught that,
but we don't have any glinda based mainboards using VBOOT in the tree
at the moment so there is no actual overlap on any upstream mainboards
at the moment. Still if VBOOT based mainboards are added in the future
it would cause a build error for them.
The next patch in the train will increase the APOB NV size properly by
increasing all the other addresses in the chain too.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4b4cb4104a59f72491a941dc1d13018f2389bb03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86861
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the PRRS object that is used in the _RST method.
Change-Id: I935fae3c215e48288d8856d7be5cacc4e261d86f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87005
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Implement logo bitmap rotation within fsp_convert_bmp_to_gop_blt() to
support devices with portrait-oriented displays. The rotation is driven
by the panel framebuffer orientation, allowing the logo to be displayed
correctly regardless of physical panel orientation.
This resolves issues where the logo was displayed incorrectly on
portrait-oriented displays.
Additionally, discard the display orientation change if the LID is
closed aka built-in display is not active. This will ensure that
display orientation is proper when extended display is attached w/o
any display rotation.
BUG=b:396580135
TEST=Verified BMP logo display in landscape mode on a portrait panel
with rotation enabled. Also verified portrait logo display in landscape
mode with rotation enabled.
Change-Id: I110bd67331f01e523c227e1a4bdb0484f0157a60
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86850
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Determine CPU frequency & voltage for use in smbios type 4 table.
Reference:
AMD PPR 57254 v1.59 Section 2.1.15 CPUID Instruction
TEST=Build for glinda SoC & verify output to reflect CPU frequency
& voltage.
Sample Output:
dmidecode -t
...
Voltage: 1.2 V
...
Current Speed: 2600 MHz
...
Change-Id: Ibd7c7f1e299a0a8d294e7e30ae3130faae16ae22
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86757
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the generic x86 SPI flash mmap driver is being used when not
using DMA and when not on GENOA. It only works for ROM_SIZE of 16 MiB
or less and prevents boot when the ROM is bigger than that.
Use the genoa_poc SPI MMAP driver on all platforms by default as it
allows to use a ROM_SIZE greater than 16MiB. The newly introduced
Kconfig SOC_AMD_COMMON_BLOCK_SPI_MMAP is used for all platforms when
the SPI DMA driver is not in use.
This doesn't allow to access the whole SPI flash using the ROM2 MMIO
window, but it no longer prevents boot when the mainboard specifies
the correct SPI flash size in Kconfig.
TEST: Booted an AMD/birman+ with 64MiB ROM specified in Kconfig.
TEST: Booted on AMD/onyx with 32MiB ROM specified in Kconfig.
Change-Id: I39e33c71d27179212ddb1f5bcca4c5d4a39d47e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86618
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add functions to return the position and size of the ROM2 and ROM3
MMIO windows that mmap the SPI flash. Starting from AMD Family 17h
Model 30h (Zen 2) the ROM3 BAR is available.
ROM3 is not supported on picasso or stoneyridge.
Document ID: 56780
TEST: Verified that both functions return sane values.
Change-Id: I10d4f0fe8a38e0ba2784a9839270d5dd3398d47a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the LPC PCI device to make sure common code builds.
Document ID: 55898
Change-Id: I52b129b47f98d88cad1d656dab4d4562c7ce3394
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86706
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 3ff85e5dcd ("soc/intel/alderlake:
Make Energy Efficient Turbo configurable") made the EnergyEfficientTurbo
User Product Data (UPD) adjustable, but it did not update the comment.
Change-Id: I34b8829efcfa3210950051e9b6d4d5a3c289ec93
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add the same wakeup method that Alder Lake uses to Meteor Lake.
Test=boot `starlabs/starbook/mtl` and check USB devices can wake.
Change-Id: I67da6af619db947ab4830fa2d9904f3e70fbfd21
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86628
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
MT8188, MT8192 and MT8195 use mt6359p RTC and share the same RTC
definitions. Move the definitions to rtc_mt6359p.h and remove duplicate
definitions.
BUG=b:391067089
TEST=build coreboot for asurada, cherry and geralt
Change-Id: I6e60148e1847171c6ab6b6dbee2fd706f3c3a47f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The MediaTek RTC driver does not check the return value of rtc_read()
and rtc_write(). Additionally, the RTC driver of recent platforms uses
void for rtc_read() and rtc_write(). Therefore, change the return type
of all rtc_{read, write} APIs to void and add assert for debugging.
BUG=b:388796896
TEST=build coreboot for elm, kukui and corsola
Change-Id: Ie5168db0abd479e63279ac4c8d6f2c668d6234f0
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MT8173, MT8183 and MT8186 read and write RTC register via pwrap
interface. Since the implementations are the same, move those APIs to a
common file.
BUG=b:388796896
TEST=build coreboot for elm, kukui and corsola
Change-Id: I6c177e8c1b5dee72c18d765f19a48eb38db121f1
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This reverts commit c476c4d5b9.
Reason for revert: Previously in CB:85799, we added a 0.5ms delay as a
workaround to solve the boot hang issue of non-serial firmware. Now that
the root cause has been identified and fixed in CB:86859, we can revert
the workaround.
Original change's description:
CB:85799, commit c476c4d5b9 ("soc/mediatek/mt8196: Delay 0.5ms after
enabling PMIF SPMI SW interface")
BRANCH=rauru
BUG=b:341054056
TEST=Build pass.
Change-Id: I0abdcae95924c4d3197496c14d20502b08938d76
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Currently, we don't explicitly disable the PMIF and SPMI resets after
the reset is completed, causing them to remain asserted for
approximately 0.5ms. That would cause the DUT to hang during PMIF
initialization (pmif_spmi_init) when using non-serial firmware.
To fix this issue, explicitly disable the PMIF and SPMI resets
immediately after the reset.
BRANCH=rauru
BUG=b:341054056
TEST=Build pass, non-serial firmware boot ok.
Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: Ic903ddd893470cd46dbfed9c3faa9c2a9e50c904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86859
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PSP_SOFTFUSE_BITs were probably copy&pasted during initial
SoC bringup and need to be adjusted:
* Drop PSP_SOFTFUSE_BIT BIT28 as it causes PSP to hang.
* Drop PSP_SOFTFUSE_BIT BIT34 as it's not required.
This also moves coreboot closer to the UEFI reference firmware.
Document #55758 Rev. 2.04
TEST: Booted on amd/birman_plus with default PSP_SOFTFUSE_BITS.
Change-Id: Ic7b2b0ac01fe0ac0ed2535254f242a8068f9b02a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86840
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
This reverts commit 07dd73c921.
Jasperlake FSP does not properly support the crashlog feature, and
enabling it results in several issues (increased boot time, issues
with USB device detection).
Change-Id: I5598b40321b3ca15a48ac6eff64a85323d55939d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Use the newly-created ACPI device in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.
Change-Id: Ie4d9a480152fabb93d784b338c2846feba874f4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Use the newly-created ACPI devices in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.
Change-Id: Id7b68e7c5ed554639dc14e837e311552c3ff92f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Use the newly-created ACPI devices in common/acpi, and adjust the
SoC ACPI name for the CSE/HECI device to match.
Change-Id: I3a4b122b206cb1fc98e693973f2aeb28e8b2ff22
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86814
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up Energy Efficient Turbo to devicetree so it can be configured.
The default value of 0 will ensure this doesn't change existing boards.
Change-Id: I58a9877371ec66e71cee15aced2413a282416b5c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86855
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This should be set to the opposite of lockdown_by_fsp.
Change-Id: I9e3c8f03ca14d2cb28c3f2f9bd74618d81e53d2c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86854
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TCO SMI handler clears the watchdog timeout flag unconditionally.
Since the system is only rebooted if the flag is already set and the
watchdog timer expires again, this means that the reboot never occurs.
This change preserves the timeout flag if CONFIG_ACPI_WDAT_WDT is
enabled, otherwise the behavior remains unchanged.
TEST=Build CB with CONFIG_ACPI_WDAT_WDT=y and
CONFIG_USE_PM_ACPI_TIMER=y, trigger the watchdog under Linux
with "wdctl -s 5 && cat > /dev/watchdog" and wait approximately 10
seconds (two watchdog periods) for the watchdog to reboot the system.
Change-Id: I2d35a8f8bcbcc3aaaadcc936fab028641dfd6e2c
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84875
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
FW Init Complete is a prerequisite for sending the FW FEATURE SHIPMENT
TIME STATE OVERRIDE message. Unfortunately, on some platforms such as
Lenovo ThinkCentre M700 Tiny, it takes too long for the flag to be set,
so enabling PTT fails.
Wait up to 5 seconds for the FW Init Complete to be set instead of
failing immediately.
On M700 Tiny with debug level set to ERROR, we have to wait nearly 2
seconds:
[EMERG] HECI: CSE took 1900 ms to complete FW init
Because FW Init Complete is not required for getting the current feature
enablement state, only for setting, move the FW Init Complete check to
after we've determined if we actually need to change the state. This
avoids needlessly increasing boot time.
Reference: Intel ME 11.x BIOS Specification, #549522, section 6.3.15
Change-Id: Ib6de170f3f998273bec437848faa49652f013f45
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84862
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Coolstar's Windows drivers require the IOM device to be visible to the
OS, so add a Kconfig to control this, which mainboards will select in
subsequent patches.
TEST=build/boot Win11 on rex/screebo, verify USB4 drivers functional.
Change-Id: I00ef9703179d87b7b476ef18d8d02fcafa9e14ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86792
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Use already defined macros in `spd.h`, ddr3.h`and `ddr4.h`.
TEST=Built google/cyan (Cyan) with BUILD_TIMELESS=1, no change in output
ROM.
Change-Id: I727aa38236ad97f9c529389fdb7d7d11c1db08d0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82314
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add EnableTcssCovTypeA and MappingPchXhciUsbA to repurpose the
integrated USB Type-C subsystem (TCSS) ports to USB3.2 Gen2x1 Type-A.
For example, to enable port 1 to be configured as USB Type-A, add the
following code in overridetree.cb:
register "enabletcsscovtypea[1]" = "true"
register "mappingpchxhciusba[1]" = "2"
AP log:
[SPEW ] EnableTcssCovTypeA[0]= 0x00000000
[SPEW ] MappingPchXhciUsbA[0]= 0x00000000
[SPEW ] EnableTcssCovTypeA[1]= 0x00000001
[SPEW ] MappingPchXhciUsbA[1]= 0x00000002
Reference document:
742076_ADL_TypeA_Repurpose_TCSS_Ports_USB3p2_Gen2x1_TWP_Rev1p2.pdf
BUG=b:400809281
TEST=Able to build and boot google/Riven
Change-Id: I3684fdf23706cec86c6da2b409aa4fbb33f4ec2e
Signed-off-by: Lawrence <lawrence.chang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86781
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
