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soc/mediatek: Refactor rtc_{read, write} for mt8173, mt8183 and mt8186

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MT8173, MT8183 and MT8186 read and write RTC register via pwrap
interface. Since the implementations are the same, move those APIs to a
common file.

BUG=b:388796896
TEST=build coreboot for elm, kukui and corsola

Change-Id: I6c177e8c1b5dee72c18d765f19a48eb38db121f1
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Yidi Lin 2025-03-19 15:19:42 +08:00
commit 114af7f95f
7 changed files with 38 additions and 72 deletions
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26
src/soc/mediatek/common/rtc_pwrap_ops.c Normal file
View file

@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/pmic_wrap_common.h>
#include <soc/rtc.h>
s32 rtc_read(u16 addr, u16 *rdata)
{
s32 ret;
ret = pwrap_read(addr, rdata);
if (ret < 0)
rtc_info("pwrap_read failed: ret=%d\n", ret);
return ret;
}
s32 rtc_write(u16 addr, u16 wdata)
{
s32 ret;
ret = pwrap_write(addr, wdata);
if (ret < 0)
rtc_info("pwrap_write failed: ret=%d\n", ret);
return ret;
}

4
src/soc/mediatek/mt8173/Makefile.mk
View file

@ -48,7 +48,7 @@ romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c
romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c
romstage-y += ../common/wdt.c ../common/reset.c
romstage-y += ../common/mmu_operations.c mmu_operations.c
romstage-y += ../common/rtc.c rtc.c
romstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c rtc.c
################################################################################
@ -66,7 +66,7 @@ ramstage-y += da9212.c
ramstage-y += ../common/gpio.c gpio.c
ramstage-y += ../common/wdt.c ../common/reset.c
ramstage-y += ../common/pll.c pll.c
ramstage-y += ../common/rtc.c rtc.c
ramstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c rtc.c
ramstage-y += ../common/usb.c usb.c

24
src/soc/mediatek/mt8173/include/soc/rtc.h
View file

@ -102,27 +102,7 @@ enum {
/* external API */
int rtc_init(int recover);
void rtc_boot(void);
static inline s32 rtc_read(u16 addr, u16 *rdata)
{
s32 ret;
ret = pwrap_read(addr, rdata);
if (ret < 0)
rtc_info("pwrap_read failed: ret=%d\n", ret);
return ret;
}
static inline s32 rtc_write(u16 addr, u16 wdata)
{
s32 ret;
ret = pwrap_write(addr, wdata);
if (ret < 0)
rtc_info("pwrap_write failed: ret=%d\n", ret);
return ret;
}
s32 rtc_read(u16 addr, u16 *rdata);
s32 rtc_write(u16 addr, u16 wdata);
#endif /* SOC_MEDIATEK_MT8173_RTC_H */

4
src/soc/mediatek/mt8183/Makefile.mk
View file

@ -38,7 +38,7 @@ romstage-y += ../common/gpio_eint_v1.c ../common/gpio.c gpio.c
romstage-y += ../common/mmu_operations.c mmu_operations.c
romstage-y += ../common/pll.c pll.c
romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c
romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
romstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c ../common/rtc_osc_init.c rtc.c
romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
romstage-y += ../common/i2c.c i2c.c
romstage-y += ../common/timer.c
@ -56,7 +56,7 @@ ramstage-y += ../common/mcu.c
ramstage-y += ../common/mmu_operations.c mmu_operations.c
ramstage-y += ../common/mtcmos.c mtcmos.c
ramstage-y += ../common/pmic_wrap.c
ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
ramstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c ../common/rtc_osc_init.c rtc.c
ramstage-y += soc.c
ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
ramstage-y += spm.c

24
src/soc/mediatek/mt8183/include/soc/rtc.h
View file

@ -85,27 +85,7 @@ bool rtc_gpio_init(void);
void rtc_boot(void);
u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
void mt6358_dcxo_disable_unused(void);
static inline s32 rtc_read(u16 addr, u16 *rdata)
{
s32 ret;
ret = pwrap_read(addr, rdata);
if (ret < 0)
rtc_info("pwrap_read failed: ret=%d\n", ret);
return ret;
}
static inline s32 rtc_write(u16 addr, u16 wdata)
{
s32 ret;
ret = pwrap_write(addr, wdata);
if (ret < 0)
rtc_info("pwrap_write failed: ret=%d\n", ret);
return ret;
}
s32 rtc_read(u16 addr, u16 *rdata);
s32 rtc_write(u16 addr, u16 wdata);
#endif /* SOC_MEDIATEK_MT8183_RTC_H */

4
src/soc/mediatek/mt8186/Makefile.mk
View file

@ -31,7 +31,7 @@ romstage-y += ../common/mt6315.c mt6315.c
romstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c
romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
romstage-y += ../common/pmif_spmi.c pmif_spmi.c
romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
romstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c ../common/rtc_osc_init.c rtc.c
ramstage-y += adsp.c
ramstage-y += ../common/auxadc.c
@ -48,7 +48,7 @@ ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
ramstage-y += ../common/mtcmos.c mtcmos.c
ramstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c
ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
ramstage-y += ../common/rtc.c ../common/rtc_pwrap_ops.c ../common/rtc_osc_init.c rtc.c
ramstage-y += soc.c
ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c
ramstage-y += ../common/sspm.c

24
src/soc/mediatek/mt8186/include/soc/rtc.h
View file

@ -89,27 +89,7 @@ int rtc_init(int recover);
bool rtc_gpio_init(void);
void rtc_boot(void);
u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
static inline s32 rtc_read(u16 addr, u16 *rdata)
{
s32 ret;
ret = pwrap_read(addr, rdata);
if (ret)
rtc_info("pwrap_read failed: ret=%d\n", ret);
return ret;
}
static inline s32 rtc_write(u16 addr, u16 wdata)
{
s32 ret;
ret = pwrap_write(addr, wdata);
if (ret)
rtc_info("pwrap_write failed: ret=%d\n", ret);
return ret;
}
s32 rtc_read(u16 addr, u16 *rdata);
s32 rtc_write(u16 addr, u16 wdata);
#endif /* SOC_MEDIATEK_MT8186_RTC_H */