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soc/amd/glinda: Fix PSP_SOFTFUSE_BITS

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The PSP_SOFTFUSE_BITs were probably copy&pasted during initial
SoC bringup and need to be adjusted:

* Drop PSP_SOFTFUSE_BIT BIT28 as it causes PSP to hang.
* Drop PSP_SOFTFUSE_BIT BIT34 as it's not required.

This also moves coreboot closer to the UEFI reference firmware.

Document #55758 Rev. 2.04
TEST: Booted on amd/birman_plus with default PSP_SOFTFUSE_BITS.

Change-Id: Ic7b2b0ac01fe0ac0ed2535254f242a8068f9b02a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86840
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
This commit is contained in:
Patrick Rudolph 2025-03-12 08:31:56 +01:00 • committed by Matt DeVillier
commit 0b03ecbc44
1 changed files with 1 additions and 1 deletions
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2
src/soc/amd/glinda/Kconfig
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@ -356,7 +356,7 @@ config PSP_WHITELIST_FILE
config PSP_SOFTFUSE_BITS
string "PSP Soft Fuse bits to enable"
default "34 28 6"
default "6"
help
Space separated list of Soft Fuse bits to enable.
Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)