Yidi Lin 114af7f95f soc/mediatek: Refactor rtc_{read, write} for mt8173, mt8183 and mt8186 ... MT8173, MT8183 and MT8186 read and write RTC register via pwrap interface. Since the implementations are the same, move those APIs to a common file. BUG=b:388796896 TEST=build coreboot for elm, kukui and corsola Change-Id: I6c177e8c1b5dee72c18d765f19a48eb38db121f1 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>		2025-03-21 08:01:18 +00:00
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amd	soc/amd/glinda: Fix PSP_SOFTFUSE_BITS	2025-03-18 19:25:24 +00:00
cavium	soc/cavium: Fix non matching types	2024-08-30 07:34:47 +00:00
example/min86
ibm/power9	3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER	2024-09-06 13:55:50 +00:00
intel	Revert "soc/intel/jasperlake: Add CrashLog implementation for Intel JSL"	2025-03-17 20:21:04 +00:00
mediatek	soc/mediatek: Refactor rtc_{read, write} for mt8173, mt8183 and mt8186	2025-03-21 08:01:18 +00:00
nvidia	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
qualcomm	soc/qualcomm/cmn/qclib: Replace magic number with BIT() macro	2025-03-13 19:22:52 +00:00
rockchip	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
samsung	samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'	2025-01-15 08:32:16 +00:00
sifive	tree: Remove unused <assert.h>	2024-11-19 00:40:04 +00:00
ti	soc/ti/am335x: Remove superfluous formats	2024-08-02 14:45:13 +00:00
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00