soc/mediatek/mt8189: Add DRAM calibration support
Add DRAM calibration support for mt8189. DRAM parameters and related
constants are added in dramc_param.h and dramc_soc.h.
The common emi.c can be reused for MT8189 as well, so remove the
duplicate mt8189/emi.{c,h}.
Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast
calibration via the DRAM blob.
BUG=b:379008996
BRANCH=none
TEST=Boot up pass and see log
3200 LPDDR5 chan0(x16) rank0: memory test pass
3200 LPDDR5 chan0(x16) rank1: memory test pass
3200 LPDDR5 chan1(x16) rank0: memory test pass
3200 LPDDR5 chan1(x16) rank1: memory test pass
Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: Ia6f6e5afc1f4a2e919243bda0799712cd7b4d01f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit is contained in:
Mike Lin
Matt DeVillier
parent
da5f4de090
commit
ec65e34332
6 changed files with 197 additions and 21 deletions
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@ -8,6 +8,9 @@ config SOC_MEDIATEK_MT8189
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select ARCH_ROMSTAGE_ARMV8_64
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select ARCH_RAMSTAGE_ARMV8_64
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select HAVE_UART_SPECIAL
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select CACHE_MRC_SETTINGS
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select MEDIATEK_DRAM_BLOB_FAST_INIT
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select USE_CBMEM_DRAM_INFO
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select SOC_MEDIATEK_COMMON
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select FLASH_DUAL_IO_READ
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select ARM64_USE_ARCH_TIMER
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@ -13,15 +13,30 @@ bootblock-y += ../common/mmu_operations.c
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bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
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romstage-y += ../common/cbmem.c
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romstage-y += emi.c
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romstage-y += ../common/dram_init.c
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romstage-y += ../common/dramc_param.c
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romstage-y += ../common/emi.c
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romstage-y += ../common/memory.c ../common/memory_test.c
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romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
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ramstage-y += emi.c
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ramstage-y += ../common/emi.c
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ramstage-y += ../common/memory.c
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ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
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ramstage-y += soc.c
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ramstage-y += ../common/usb.c usb.c
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CPPFLAGS_common += -Isrc/soc/mediatek/mt8189/include
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CPPFLAGS_common += -Isrc/soc/mediatek/common/include
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MT8189_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8189
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DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram
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$(DRAM_CBFS)-file := $(MT8189_BLOB_DIR)/dram.elf
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$(DRAM_CBFS)-type := stage
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$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
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ifneq ($(wildcard $($(DRAM_CBFS)-file)),)
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cbfs-files-y += $(DRAM_CBFS)
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endif
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$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
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./util/mtkheader/gen-bl-img.py mt8189 sf $< $@
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@ -1,8 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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#include <soc/emi.h>
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size_t sdram_size(void)
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{
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return (size_t)4 * GiB;
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}
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116
src/soc/mediatek/mt8189/include/soc/dramc_param.h
Normal file
116
src/soc/mediatek/mt8189/include/soc/dramc_param.h
Normal file
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@ -0,0 +1,116 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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#ifndef __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__
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#define __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__
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/*
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* NOTE: This file is shared between coreboot and dram blob. Any change in this
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* file should be synced to the other repository.
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*/
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#include <soc/dramc_param_common.h>
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#include <soc/dramc_soc.h>
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#include <stdint.h>
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#include <sys/types.h>
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#define DRAMC_PARAM_HEADER_VERSION 1
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#define CATRAINING_NUM_LP5 7
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struct sdram_params {
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/* rank, cbt */
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u32 rank_num;
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u32 dram_cbt_mode;
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u16 delay_cell_timex100;
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u8 u18ph_dly[CHANNEL_MAX];
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/* duty */
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s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
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s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
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s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
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s8 duty_mck16x_delay[CHANNEL_MAX][DQS_NUMBER_LP5 + 1];
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s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
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s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
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/* cbt */
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u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
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u8 cbt_final_range[CHANNEL_MAX][RANK_MAX];
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s16 s2CBTCAWindow_first_pass_Save[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP5];
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s16 s2CBTCAWindow_last_pass_Save[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP5];
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s16 cbt_cmd_dly[CHANNEL_MAX];
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u16 cbt_cs_dly[CHANNEL_MAX];
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u8 cbt_ca_prebit_dly[CHANNEL_MAX][DQS_BIT_NUMBER];
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/* write leveling */
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u8 wr_level_pi[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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u8 wr_level_dly[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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/* gating */
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u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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u16 wck2dqo_cnt[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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/* rx input buffer */
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s8 dq_offc[CHANNEL_MAX][DQ_DATA_WIDTH_LP5];
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s8 dqm_offc[CHANNEL_MAX][DQS_NUMBER_LP5];
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/* tx perbit */
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u16 tx_window_vref[CHANNEL_MAX][RANK_MAX];
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u16 tx_window_vref_range[CHANNEL_MAX][RANK_MAX];
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s16 u1Txfirst_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
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s16 u1Txlast_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
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u16 tx_dq[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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u16 tx_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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u16 tx_dqm_only[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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u8 tx_perbit_dlyline[CHANNEL_MAX][RANK_MAX][EXT_DQ_DATA_WIDTH];
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u16 wck2dqi_cnt0[CHANNEL_MAX][RANK_MAX];
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u16 wck2dqi_cnt1[CHANNEL_MAX][RANK_MAX];
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/* rx datlat */
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u8 rx_datlat[CHANNEL_MAX];
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/* rx perbit */
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u8 rx_best_vref_perbyte[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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//u8 rx_best_vref_perbit[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
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s16 u1Rxfirst_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
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s16 u1Rxlast_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
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u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
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s16 rx_perbit_begin;
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/* dvs */
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u8 dvs_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
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u8 perbit_dcc[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
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/* dcm */
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u8 best_u[CHANNEL_MAX][RANK_MAX];
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u8 best_l[CHANNEL_MAX][RANK_MAX];
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/* Read DCA */
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s8 rdca_u[CHANNEL_MAX][RANK_MAX];
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s8 rdca_l[CHANNEL_MAX][RANK_MAX];
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/* RDCC */
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s8 rdcc[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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/* tx oe */
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u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
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u16 tx_oe_offset[CHANNEL_MAX][RANK_MAX];
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};
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struct dramc_data {
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struct ddr_base_info ddr_info;
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struct sdram_params freq_params[DRAM_DFS_SHU_MAX];
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};
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struct dramc_param {
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struct dramc_param_header header;
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void (*do_putc)(unsigned char c);
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struct dramc_data dramc_datas;
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};
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#endif /* __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__ */
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60
src/soc/mediatek/mt8189/include/soc/dramc_soc.h
Normal file
60
src/soc/mediatek/mt8189/include/soc/dramc_soc.h
Normal file
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@ -0,0 +1,60 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__
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#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__
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#include <soc/dramc_soc_common.h>
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#include <stdint.h>
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typedef enum {
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CHANNEL_A = 0,
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CHANNEL_B,
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CHANNEL_MAX,
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} DRAM_CHANNEL_T;
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typedef enum {
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RANK_0 = 0,
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RANK_1,
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RANK_MAX,
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} DRAM_RANK_T;
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typedef enum {
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SRAM_SHU0 = 0,
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SRAM_SHU1,
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SRAM_SHU2,
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SRAM_SHU3,
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SRAM_SHU4,
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DRAM_DFS_SRAM_MAX
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} DRAM_DFS_SRAM_SHU_T; /* DRAM SRAM RG type */
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typedef enum {
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DRVP = 0,
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DRVN,
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ODTN,
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IMP_DRV_MAX,
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} DRAM_IMP_DRV_T;
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typedef enum {
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TYPE_INVALID = 0,
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TYPE_DDR1,
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TYPE_DDR2,
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TYPE_DDR3,
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TYPE_DDR4,
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TYPE_DDR5,
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TYPE_LPDDR2,
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TYPE_LPDDR3,
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TYPE_PCDDR3,
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TYPE_LPDDR4,
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TYPE_LPDDR4X,
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TYPE_LPDDR4P,
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TYPE_LPDDR5,
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TYPE_LPDDR5X,
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TYPE_MAX,
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} DRAM_DRAM_TYPE_T;
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#define DRAM_DFS_SHU_MAX DRAM_DFS_SRAM_MAX
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#define DQS_NUMBER_LP5 2
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#define DQ_DATA_WIDTH_LP5 16
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#define EXT_DQ_DATA_WIDTH 18
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#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__ */
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@ -1,10 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__
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#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__
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#include <stddef.h>
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size_t sdram_size(void);
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#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ */
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