soc/amd/common/psp_verstage: Remove arch/io.h

The arch include files are overshadowed by PSP verstage include files.
The reason is that psp_verstage implements its own set of inb() and
outb() functions, which use a runtime configurable IO base address
instead of a built time constant.

But this works at the moment only because of the order in which the
include files are added. Since that is very error prone, this patch
introduces another solution to the problem.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I16fa4a4cb5168024aaef30119e9aa8a34dbaacbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/device/Kconfig

@@ -558,12 +558,6 @@ config PCI
 	bool
 	default n
 
-config PCI_IOBASE
-	hex
-	help
-	  The memory address of a memory-mapped translator that lets the
-	  CPU communicate with peripheral devices over PCI I/O space.
-
 if PCI
 
 config DOMAIN_RESOURCE_32BIT_LIMIT

src/include/arch-generic/io.h

@@ -19,7 +19,12 @@
 #include <endian.h>
 #include <arch/mmio.h>
 
-#define __io(a)	(void *)(uintptr_t)(CONFIG_PCI_IOBASE + a)
+/*
+ * The memory address of a memory-mapped translator that lets the
+ * CPU communicate with peripheral devices over PCI I/O space.
+ */
+extern uintptr_t io_port_mmio_base;
+#define __io(a) (void *)(io_port_mmio_base + a)
 
 static inline void outb(uint8_t value, uint16_t port)
 {

src/lib/Makefile.mk

@@ -291,6 +291,10 @@ postcar-y += rmodule.c
 postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 postcar-$(CONFIG_GENERIC_UDELAY) += timer.c
 
+all-$(CONFIG_ARCH_ARM) += io.c
+all-$(CONFIG_ARCH_ARM64) += io.c
+all-$(CONFIG_ARCH_RISCV) += io.c
+
 # Use program.ld for all the platforms which use C fo the bootblock.
 bootblock-y += program.ld
 

src/lib/io.c

@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+
+uintptr_t __weak io_port_mmio_base = 0;

src/mainboard/emulation/qemu-aarch64/Kconfig

@@ -30,9 +30,6 @@ config ECAM_MMCONF_BASE_ADDRESS
 config ECAM_MMCONF_BUS_NUMBER
 	default 256
 
-config PCI_IOBASE
-	default 0x3eff0000
-
 config MEMLAYOUT_LD_FILE
 	string
 	default "src/mainboard/emulation/qemu-aarch64/memlayout.ld"

src/mainboard/emulation/qemu-aarch64/mmio.c

@@ -3,6 +3,8 @@
 #include <console/uart.h>
 #include <mainboard/addressmap.h>
 
+uintptr_t io_port_mmio_base = 0x3eff0000;
+
 uintptr_t uart_platform_base(unsigned int idx)
 {
 	return VIRT_UART_BASE;

src/soc/amd/common/psp_verstage/fch.c

@@ -48,21 +48,11 @@ static void gpio_set_bar(void *bar)
 	acpimmio_gpio0 = bar;
 }
 
-static uintptr_t io_bar;
+uintptr_t io_port_mmio_base;
 
 static void io_set_bar(void *bar)
 {
-	io_bar = (uintptr_t)bar;
-}
-
-u8 io_read8(u16 reg)
-{
-	return read8p(io_bar + reg);
-}
-
-void io_write8(u16 reg, u8 value)
-{
-	write8p(io_bar + reg, value);
+	io_port_mmio_base = (uintptr_t)bar;
 }
 
 static void aoac_set_bar(void *bar)

src/soc/amd/common/psp_verstage/include/arch/io.h

@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __ARCH_IO_H__
-#define __ARCH_IO_H__
-
-#include <stdint.h>
-
-u8 io_read8(u16 reg);
-void io_write8(u16 reg, u8 value);
-
-static inline void outb(uint8_t value, uint16_t port)
-{
-	io_write8(port, value);
-}
-
-static inline uint8_t inb(uint16_t port)
-{
-	return io_read8(port);
-}
-
-#endif