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soc/amd/glinda/Kconfig: Increase APOB NV size

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A glinda based platform reports:
[WARN] RAM APOB data is too large (3b3b0 + 8) > 1e000

APOB NV size is not enough on recent platforms to cache memory training,
which causes the same amount of boot time on subsequent boots as on the
first boot.

This time increase the size properly by adjusting the base address of
the components that come after the APOB region.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I070cf766b98825cd5ff37674e1f9651fa71159c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Maximilian Brune 2025-03-12 22:48:14 +01:00 • committed by Felix Held
commit a38cb1bd43
5 changed files with 9 additions and 9 deletions
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2
src/mainboard/amd/birman/board_glinda.fmd
View file

@ -4,6 +4,6 @@ FLASH@0xFF000000 16M {
FMAP 4K
COREBOOT(CBFS)
EC_BODY@15872K 256K
RW_MRC_CACHE 120K
RW_MRC_CACHE 256K
}
}

2
src/mainboard/amd/birman/chromeos_glinda.fmd
View file

@ -30,6 +30,6 @@ FLASH@0xFF000000 16M {
SMMSTORE(PRESERVE) 256K
RW_LEGACY(CBFS)
EC_BODY@15872K 256K
RW_MRC_CACHE(PRESERVE) 120K
RW_MRC_CACHE(PRESERVE) 256K
}
}

2
src/mainboard/amd/birman_plus/board_glinda.fmd
View file

@ -5,6 +5,6 @@ FLASH 64M {
COREBOOT(CBFS)
SMMSTORE(PRESERVE) 256K
EC_BODY@15872K 256K
RW_MRC_CACHE 120K
RW_MRC_CACHE 256K
}
}

2
src/mainboard/amd/birman_plus/chromeos_glinda.fmd
View file

@ -30,6 +30,6 @@ FLASH@0xFF000000 16M {
SMMSTORE(PRESERVE) 256K
RW_LEGACY(CBFS)
EC_BODY@15872K 256K
RW_MRC_CACHE(PRESERVE) 120K
RW_MRC_CACHE(PRESERVE) 256K
}
}

10
src/soc/amd/glinda/Kconfig
View file

@ -123,11 +123,11 @@ config PSP_APOB_DRAM_ADDRESS
config PSP_APOB_DRAM_SIZE
hex
default 0x1E000
default 0x40000
config PSP_SHAREDMEM_BASE
hex
default 0x201F000 if VBOOT
default 0x2041000 if VBOOT
default 0x0
help
This variable defines the base address in DRAM memory where PSP copies
@ -172,7 +172,7 @@ config C_ENV_BOOTBLOCK_SIZE
config ROMSTAGE_ADDR
hex
default 0x2050000
default 0x2070000
help
Sets the address in DRAM where romstage should be loaded.
@ -184,7 +184,7 @@ config ROMSTAGE_SIZE
config FSP_M_ADDR
hex
default 0x20C0000
default 0x20E0000
help
Sets the address in DRAM where FSP-M should be loaded. cbfstool
performs relocation of FSP-M to this address.
@ -204,7 +204,7 @@ config FSP_TEMP_RAM_SIZE
config VERSTAGE_ADDR
hex
depends on VBOOT_SEPARATE_VERSTAGE
default 0x2180000
default 0x21A0000
help
Sets the address in DRAM where verstage should be loaded if running
as a separate stage on x86.