1158e26a26
Since FSP doesn't support disabling bridges and has no UPDs for that, they must be enabled in DT to make sure they are properly initialized during PCI enumeration as expected by the payload (EDK2 for example). It might be OK to have them set to off when all devices behind the bridge are also off and FSP disables those secondary devices. In general something that cannot be hidden/shut off shouldn't be marked as such, as later stages (payload/OS) might find it active, but unconfigured. Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> |
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| cavium | ||
| example/min86 | ||
| ibm/power9 | ||
| intel | ||
| mediatek | ||
| nvidia | ||
| qualcomm | ||
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| samsung | ||
| sifive | ||
| ti | ||
| ucb/riscv | ||
| xilinx | ||