Also add an interface for printing macros to override this in the test
and not create a new gpio file for comparison.
Change-Id: I16c9b4451cd4418b49043a925cb879a982a56461
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67701
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drobit shows little power usage (around 9W) and very low clock speeds
(1.1GHz - 1.4GHz) under load (`stress -c $(nproc)`), despite being at
temperature too low for thermal throttling (40-50C). It turns out that
power_limits_config is set to the lower end of the dptf power limit
ranges as opposed to baseboard and other variants. This seems to
prevent the device from using the intended power limits.
Tested: Boot and confirm more reasoable power usage (17W) and clock
speeds (around 2.5GHz) as well as good temperatures (topped 85C) and
stability under 100% load (`stress -c $(nproc)` for 30min).
Device for tests is i5-1135G7 and 16GG RAM.
Change-Id: Id0478c713b51db4972e7d93ec597a30fa885c22b
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86026
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some keyboard controllers need to have a specific bit in the command
byte set (e.g. PC_KBC_TRANSLATE) in order for the keyboard to function
properly.
Change-Id: I8745d1848f223634043eecc4659021a76a2b239b
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85330
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On x86_32 the xHCI BAR isn't reachable as it's mapped in high MMIO.
Currently this is not a problem since the code is unused.
Add a check and return NULL instead of cutting of the higher bits
and thus do not return an invalid pointer. On x86_64 it's working
when the extended page-tables are installed.
Change-Id: I00496ad476c33e0984d7cb0019f27154302edda5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
On Xeon Skylake-SP with dual sockets the platforms make use of 46bit of
the address space. Most of the PCI BARs reside in high MMIO, not
reachable by x86_32 coreboot.
Add support for x86_64 coreboot and confirm that all supported boards
are booting without errors. This is done by:
- converting all occurrences of VOID * to UINT32 to make sure that
FSP UPDs do not change when pointers are 8byte wide.
- Drop SetupStructPtr as it's unused within FSP and coreboot
TEST: Booted on ocp/tiogapass to Linux. No errors were observed.
Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Document the board and how to flash coreboot.
Change-Id: Id585b064054b338ea8cead6edb6c5153030b9cde
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Document the board and process of building/flashing coreboot on it.
Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81611
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On vendor firmware, the IFD is read-only and ME completely locked. But
the BIOS region can be internally flashed with coreboot. Super I/O GP15
is connected to HDA_SDO, potentially enabling write access to entire
flash. Simply setting this GPIO, and restarting the board wasn't enough.
Tested:
- i5-2500K
- 8GB or 2x8GB Hynix HMT41GS6BFR8A-RD (@1333MHz)
- 8+4GB Hynix HMT351S6EFR8A-PB (@1333MHz)
- Internal SATA ports
- Realtek Ethernet
- libgfxinit, onboard DVI
- All rear USB and USB3 ports, internal Bluetooth dongle is detected
- SeaBIOS boots to Void Linux and Devuan
- PS/2 keyboard and mouse (only combo port, one at a time)
- PEG slot
- Mini-PCIe WLAN slot
Not tested:
- eSATA
- SPDIF
- LEDs: front panel
Not working:
- Super I/O shows weird temperatures in lm_sensors: CPU -51°C AUX +84°C
- Resuming from S3 when root partition is on an USB 3.0 stick (works
when it's attached to USB 2.0 or SATA).
- DRAM_LED (on vendor firmware, it stays lit if there are DRAM problems)
Change-Id: I7de37a5cb8bf8d44253fe3418ffc9e07caca9703
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
The fw_cfg device can be used by other qemu boards outside i440fx (and
q35, which manually includes the code). Factor out the fw_cfg code as a
separate driver that qemu mainboards can enable.
Change-Id: I8c5c4cb5f5478abd21aab8e8d0b503db41d81d40
Signed-off-by: Carlos López <carlos.lopez@openchip.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85673
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since commit 943b540914 USB configurations are read from the
southbridge devicetree
This change only moves the USB configuration from early_init.c to
the devicetree
Change-Id: I69f1f800e4e2de5367795400d619bf9c000ff184
Signed-off-by: Vesek <venda.straka@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85831
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop MRC setting usb3.hs_port_switch_mask that since commit ee12634872
("nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetree")
mirrors xhci_switchable_ports and is no longer used separately.
Change-Id: Ic1937461ab45f74f29521a8692629290bfd3c560
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85821
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop PCI(e) devices from devicetree that remain off or unchanged from
chipset defaults.
TEST=Timeless binaries did not change across entire family.
Change-Id: I4feb88a78f72952bed049505073aed00d2120df3
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85797
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the aliases are used and already contain the device name,
there's reason to generate these in the first place.
TEST=Ran autoport with logs from ASRock Z77 Extreme4.
Change-Id: I3378801f5a997a802da61f2b7c4e820f39064019
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85822
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based mostly on the comments in the file. Physical slot lengths
checked from manufacturer's specs online.
TEST: It still builds
Change-Id: I706910dd192ca3415082955a7611d17702d3cfba
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Customers have asked that the NPU device be available.
Test: Verified the device shows up in lspci.
Change-Id: I2b5c3030c6378c0998a2ac792126c15d2e17bbf9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85721
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds device id for Crashlog and Telemetry. CPU crashlog
record is stored in punit SRAM.
Source: EDS 815002
BUG=None
TEST=Build fatcat and boot with Panther Lake SoC with added
device id.
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Change-Id: I2959623986108a2c5e3dce16e892913a42d71755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
A timeout when attempting to read/write to an EC should be treated as
an error, as it could potentially cause unwanted or unexpected behavior
from the device.
Change-Id: I60be6191dcd8ff576fa525f08720b6ea2d0a7454
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This is now copied from USBOCM1 built with main USB port config.
Boards patched here have matching EHCI and xHCI overcurrent mappings.
Change-Id: I36944e2f2ed265ee492019b75b7dd8b95ca26dbb
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
BUG=b:317009620
TEST=Build passed, boot successful. Verified that the available CPU
frequency ranges are correct using the command:
cat /sys/devices/system/cpu/cpufreq/policy*/scaling_available_frequencies
Change-Id: I6f290946365b4c5a650651ebea30ffc76583d2b2
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86042
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add eDP panel power-on sequences and initialize the display in the
ramstage. The mt6373_set_vcn33_3_voltage function sets the voltage
required to power on the eDP panel.
TEST=Build pass, the firmware screen displays correctly.
BUG=b:343351631, b:353464237
Signed-off-by: Nancy Lin <nancy.lin@mediatek.corp-partner.google.com>
Change-Id: Ic928b2478c41ccd03223fd2b73d9e81d303a2036
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Add panel driver in mainboard for rauru project and support OLED eDP
panel.
TEST=check edp training pass and show log:
EQ training pass
BUG=b:343351631
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Change-Id: Iea610c97351beb94a49cc1044701a523b7c85a6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
For the Q events to be used, they need to sit under the EC device
in ACPI. Move them accordingly.
Change-Id: I58a41ae660ec466a08d4c290ff820b713b866f4f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The back USB port is a data-only port without switching, so
update the ACPI configuration accordingly.
Change-Id: Ic6b77f44a2d2607d201a2b097cea41aa361ebbee
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The group number was incorrect.
Change-Id: I87928f190af2ed7fd00cb08283036aede7fd6383
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Correct the position of the word "Back" so it's the same each
interface of the port.
Change-Id: I10285c081838b358f8708a69317ba6bf3b551eb2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86082
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is NF2, not NF1.
Change-Id: Ie99903b0947165a70d260f383889421500f10b4c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set the pad to DEEP, instead of PLTRST as this is more reliable
when resuming from S3.
Change-Id: Ida3713bbbce1eb9c6793fec2172005b4dfd54e86
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These GPIO's are not used, so disconnect them or set the outputs
low accordingly.
Change-Id: I5e5f7587b59da0b91e7c247b4813c5e78d2c1313
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This was copied from `starbook/adl` and is not needed.
Change-Id: I9a234d8653c026b09411aa5b63ecba477aef325f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86074
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This board does not have a 20K Pull Down resistor fitted here,
meaning this will not change anything. However, it unifies the
the configuration with the other Star Labs boards.
Change-Id: Iee0adea21c124e0a421a1506310944cc883a73fb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These GPIO's are not used, so disconnect them.
Change-Id: I68e0c8c840c811de733775e7a6f79d9d9e91bb8c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86065
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the trace lengths as comments, and update the macros used for the
USB ports accordingly.
Like other boards, avoid the `USB2_PORT_TYPE_C` macro, as it makes
ports behave inconsistantly.
Change-Id: Id193b3ed86c58aedc7d5a1f384f2829a2bf18671
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85974
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both cameras share the same USB 2.0 interface, rather than using their
own port. Update the configuration to match this.
Change-Id: Ia2d8698394de69af53489e3a08c7fe7b4f2fbc07
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86064
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The comments are the wrong way round.
Change-Id: Ifd46cd7e633f37e57213fffee4f70a7262894100
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Since add-int is intended for manipulating options stored as integers in
CBFS (such as SeaBIOS runtime config options), removing the file so that
it can be re-added with a new value is a common action. Attempt to
remove the existing integer automatically if it already exists to remove
the need for the extra step.
Change-Id: I5a0ac409fc9b91a4f7c0c35650875d6211ac2b25
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86009
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We should be writing to the address of reg[i], instead of the address
whose value is reg[i].
Change-Id: I4fb78f974155725a91aad3a5450733d24b57af15
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
According to the EVT's circuit design changes, update the following LAN
settings:
1. set root port to 7
2. set clock source/request to 2
BUG=b:386025819
BRANCH=firmware-rex-15709.B
Change-Id: Ia8be74c601a536f1aa932dd6c14ae3f5068d0a7f
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86072
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new option backend that uses values stored in CBFS files, similar
to the SeaBIOS runtime config options stored in files with the etc/
prefix. Options should be stored in CBFS with the option/ prefix. Values
can be set using `cbfstool coreboot.rom add-int -n option/<option-name>
-i <value>`. For simplicity, options should be stored in the COREBOOT
(RO) FMAP region, which is the default for cbfstool. This backend is not
available in SMM due to CBFS dependencies on vboot functions which are
not added to SMM, and thus the fallback will be returned by calls to
get_uint_option() in SMM.
Tested with QEMU Q35 by setting various options for "sata_mode" and
observing the console output for the SATA controller mode during
i82801ix_sata initialization.
Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
