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mb/google/rex/var/kanix: Update LAN settings for EVT

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According to the EVT's circuit design changes, update the following LAN
settings:
1. set root port to 7
2. set clock source/request to 2

BUG=b:386025819
BRANCH=firmware-rex-15709.B

Change-Id: Ia8be74c601a536f1aa932dd6c14ae3f5068d0a7f
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86072
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kenneth Chan 2025-01-20 18:09:05 +08:00 • committed by Subrata Banik
commit 72630183a1
1 changed files with 5 additions and 5 deletions
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10
src/mainboard/google/rex/variants/kanix/overridetree.cb
View file

@ -572,7 +572,7 @@ chip soc/intel/meteorlake
end
end
end #PCIE5 WLAN card
device ref pcie_rp6 on
device ref pcie_rp7 on
chip drivers/net
register "wake" = "GPE0_DW1_04"
register "led_feature" = "0xe0"
@ -582,10 +582,10 @@ chip soc/intel/meteorlake
register "add_acpi_dma_property" = "true"
device pci 00.0 on end
end
# Enable PCIE 6 using clk 6
register "pcie_rp[PCH_RP(6)]" = "{
.clk_src = 6,
.clk_req = 6,
# Enable PCIE 7 using clk 2
register "pcie_rp[PCH_RP(7)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end # RTL8125 Ethernet NIC