mb/asus/p8x7x-series: Streamline devicetree configs

Drop PCI(e) devices from devicetree that remain off or unchanged from
chipset defaults.

TEST=Timeless binaries did not change across entire family.

Change-Id: I4feb88a78f72952bed049505073aed00d2120df3
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85797
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Keith Hui 2023-12-26 15:46:52 -05:00 committed by Matt DeVillier
commit 9b1ac49a49
5 changed files with 0 additions and 35 deletions

View file

@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge
# from runtime code)
device domain 0 on
device ref host_bridge on end
device ref peg10 on end # PCIEX16_1
device ref igd on end
@ -28,30 +27,10 @@ chip northbridge/intel/sandybridge
register "xhci_switchable_ports" = "0x0000000f"
device ref xhci on end
device ref mei1 on end
device ref mei2 off end
device ref me_ide_r off end
device ref me_kt off end
device ref gbe off end
device ref ehci2 on end
device ref hda on end
device ref pcie_rp1 off end
device ref pcie_rp2 off end
device ref pcie_rp3 off end
device ref pcie_rp4 off end
device ref pcie_rp5 off end
device ref pcie_rp6 off end
device ref pcie_rp7 off end
device ref pcie_rp8 off end
device ref ehci1 on end
device ref pci_bridge off end
device ref lpc on end
device ref sata1 on end # SATA (AHCI)
device ref smbus on end
device ref sata2 off end # SATA (Legacy)
device ref thermal off end
end
end
end

View file

@ -24,13 +24,9 @@ chip northbridge/intel/sandybridge
{ 1, 0, 6 }
}"
device ref pcie_rp1 on end # PCIEX16_4 (electrical x4)
device ref pcie_rp2 off end
device ref pcie_rp3 off end
device ref pcie_rp4 off end
device ref pcie_rp5 on end # PCIEX1_1
device ref pcie_rp6 on end # 82574 GbE #1
device ref pcie_rp7 on end # 82574 GbE #2
device ref pcie_rp8 off end
device ref pci_bridge on end
device ref lpc on
chip superio/nuvoton/nct6776

View file

@ -22,9 +22,6 @@ chip northbridge/intel/sandybridge
}"
register "gen1_dec" = "0x000c0291"
device ref pcie_rp1 on end # PCIEX16_2 (electrical x4)
device ref pcie_rp2 off end
device ref pcie_rp3 off end
device ref pcie_rp4 off end
device ref pcie_rp5 on end # AR8161 GbE NIC
device ref pcie_rp6 on end # ASM1083 PCI Bridge
device ref pcie_rp7 on end # PCIEX1_1

View file

@ -23,16 +23,12 @@ chip northbridge/intel/sandybridge
}"
device ref pcie_rp1 on end # PCIe x4 slot
device ref pcie_rp2 off end
device ref pcie_rp3 off end
device ref pcie_rp4 off end
device ref pcie_rp5 on end # PCIe x1 slot
device ref pcie_rp6 on # RTL8111F GbE NIC
subsystemid 0x1849 0x1e1a
device pci 00.0 on end # make onboard
end
device ref pcie_rp7 on end # PCI slot via ASM1083
device ref pcie_rp8 off end
device ref lpc on
chip superio/nuvoton/nct6779d
device pnp 2e.1 off end # Parallel

View file

@ -24,9 +24,6 @@ chip northbridge/intel/sandybridge
register "gen1_dec" = "0x000c0291"
device ref pcie_rp1 on end # PCIEX16_2 (electrical x4)
device ref pcie_rp2 off end
device ref pcie_rp3 off end
device ref pcie_rp4 off end
device ref pcie_rp5 on end # RTL8111 GbE NIC
device ref pcie_rp6 on end # ASM1083 PCI Bridge
device ref pcie_rp7 on end # PCIEX1_1