Documentation: Add Erying Polestar G613 Pro
Document the board and process of building/flashing coreboot on it. Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81611 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Alicja Michalska
Matt DeVillier
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Documentation/mainboard/erying/tgl/tgl_matx.md
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# Erying Polestar G613 Pro
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This page describes how to run coreboot on the [Erying Polestar G613 Pro].
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## Required proprietary blobs
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To build full working image of coreboot, the following blobs are required:
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```{eval-rst}
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+-----------------+---------------------------------+----------------------+
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| Binary file | Apply | Required / Optional |
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+=================+=================================+======================+
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| Microcode | CPU Microcode | Required (see notes) |
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+-----------------+---------------------------------+----------------------+
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| FSP-M & FSP-S | Intel Firmware Support Package | Required |
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+-----------------+---------------------------------+----------------------+
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| ME | Intel Management Engine | Required (see notes) |
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+-----------------+---------------------------------+----------------------+
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| FD | Intel Flash Descriptor | Required (see notes) |
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+-----------------+---------------------------------+----------------------+
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```
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Microcode for those SoCs cannot be generated from the tree.
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While boards with D1 (production) stepping may work, microcode Intel had
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included in their tree is too old, which causes issues with APIC
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(Advanced Programmable Interrupt Controller), resulting in overall instability.
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This is **required** for boards sold with D0 SoC revision (Engineering Sample).
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Maintainer of this port had included publicly-available [microcodes] in
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`3rdparty/blobs` coreboot repository, which are being pulled as submodule.
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To choose appropriate microcode for your system, you should choose:
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1. If your motherboard uses Engineering Sample (D0) stepping:
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- `cpu806D0_platC2_ver00000054_2021-05-07_PRD_B0F9E245.bin`
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2. If your motherboard uses retail (D1) stepping:
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- `cpu806D1_platC2_ver00000046_2023-02-27_PRD_08E6188A.bin`
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By going to `Chipset -> Include CPU microcode in CBFS
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(Include external microcode binary)`
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Failure to choose an appropriate microcode may result in:
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- Bricked (unbootable) board
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- Issues with APIC, resulting in random freezes
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- MCE (Machine Check Exception) errors
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- Unstable system RAM, leading to bit flips and data corruption
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There are no extra steps required for FSP.
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Both SKUs work perfectly with FSP Intel publishes in their public repository.
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coreboot automatically pulls FSP binary from `3rdparty/fsp` submodule
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at build time, which points to TigerLakeFspBinPkg/Client package in
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official Intel FSP repository.
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## Flashing coreboot
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### Internally
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Vendor of this motherboard hasn't locked any flash regions, resulting in
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[flashrom] having full access to the SPI chip.
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Assuming that user had booted Linux with `iomem=relaxed`, they can:
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- Flash coreboot from stock firmware
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- Flash stock firmware from coreboot
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- Update coreboot build to a newer version
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Without opening the case and connecting the SPI flasher.
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Please note that you will need to use [flashrom] v1.3.0 or newer,
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as older versions won't detect the chipset.
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If you're using [flashrom] or [flashprog] (fork of flashrom), you can
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skip extracting `SI_BIOS` and `SI_ME` regions from your ROM, and flash
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coreboot to `SI_BIOS` region by issuing the following command:
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`flashrom -p internal --ifd -i SI_BIOS -w ./build/coreboot.rom`
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### Externally
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SPI chip on this mainboard is located right underneath the PCH heatsink.
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Due to it's location, it's likely that you will need to move (or remove)
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the PCH (Platform Controller Hub) heatsink in order to clip it properly.
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Vendor populated this board with Winbond W25Q128FV chip in SOIC-8 package.
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Although the stock chip is 16MiB, it is possible to replace it with 32MiB
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equivalent if user desires to use LinuxBoot payload instead of EDK2.
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Please note that SPI voltage on this board is standard 3.3V,
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despite using mobile SoC and PCH.
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## Tested and working
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- RS232 serial output from IT8613E for debugging (cbmem, Linux)
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- Fan control from userspace (IT8613E Environment Controller)
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- USB2.0 and 3.0
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- HDMI (iGPU, including audio)
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- Realtek RTL8111 (GbE NIC)
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- Realtek ALC897 (integrated audio)
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- PCIe x16 4.0 (SoC)
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- PCIe x1 3.0 (PCH)
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- M.2 x4 4.0 (SoC)
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- M.2 x4 3.0 (PCH)
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- M.2 NGFF (WiFi)
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- 4x SATA3 ports
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- IOMMU/VT-x (PCIe passthrough)
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- PCIe ReBAR (Resizable BAR)
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- Intel PTT (fTPM 2.0)
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## Work in progress, broken, issues
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- XMP Profiles (some people reported issues, despite successful tests).
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You can enable it by setting `SpdProfileSelected` in `romstage_fsp_params.c`.
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See [FSP XMP flags] for configuration options, proceed with caution.
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- GOP init on external GPUs (most EDK2 branches do not include module
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necessary to load external Option ROMs)
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- Sleep states (which were broken on stock as well)
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- USB3.2 might take few tries to get detected at full speed
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- iGPU DisplayPort (very simple fix, did not have time to fix GPIO)
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- Automatic fan control (fans will always spin at 50% - see below)
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- 2x USB2.0 FP and M.2 NGFF USB2.0 not mapped (yet)
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- PCIe ASPM (results in AER spam in dmesg)
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Please ensure to:
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- Disable sleep state in your OS to prevent data loss
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- Configure automatic fan control using pwmconfig
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(`modprobe it87 force_id=0x8603`)
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- Append `pcie_aspm=off` to your kernel commandline to avoid dmesg spam.
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## Notes
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1. Required blobs, if flashing the entire flash chip.
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They can be skipped safely if you are planning on flashing
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only the `SI_BIOS` region.
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- Intel Flash Descriptor (IFD): `descriptor.bin`
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- Intel Management Engine (ME): `me.bin`
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Both blobs included in `3rdparty/blobs` repository were extracted
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from vendor's firmware (available to download on their website).
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IFD region has been modified using `ifdtool` to set
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`MeAltDisable` flag.
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2. Modifications
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It is possible to replace Winbond 16MB chip with 32MB equivalent,
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which would allow you to use LinuxBoot or implement
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RO + A/B VBOOT update scheme.
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3. Payload and pre-OS display output
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If you are using an external graphics card (AMD, Nvidia, Intel Arc),
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you will see output in your OS as soon as kernel initializes the
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card (called "modprobing" in Linux) regardless of payload you chose.
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This board was tested with following payloads:
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- EDK2
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- U-Boot
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- LinuxBoot (U-Root + Linux kernel)
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If you would like to see output on your iGPU before that stage
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(for picking a different boot medium or toggling Secure Boot setting),
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you need to use [MrChromebox's EDK2] fork and include [GOP driver] for
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TigerLake iGPU in your build.
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This will allow you to see output of EDK2 (payload, boot picker)
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on your monitor connected to iGPU.
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If you're planning to primarly use an external card, disable iGPU by
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enabling `Chipset -> Disable Integrated GFX Controller (0:2:0)`
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and use [elly's EDK2] tree.
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In order to enable loading Option ROMs from PCIe devices, go to:
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`Payload -> edk2 additional custom build parameters`
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and add the string: `-D LOAD_OPTION_ROMS=TRUE`
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This functionality has been tested with following graphics cards,
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with following results:
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- Nvidia GeForce RTX3080, RTX3090: Works perfectly
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- AMD Radeon RX6600XT, RX7800XT: Works with ReBAR disabled,
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no output in EDK2 with ReBAR enabled
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- Intel Arc A580: Works with ReBAR disabled,
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corrupted framebuffer before modprobing with ReBAR enabled
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## Specification
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```{eval-rst}
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+------------------+------------------------------+
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| SoC | Intel TigerLake Halo |
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+------------------+------------------------------+
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| PCH | Intel HM570 |
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+------------------+------------------------------+
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| Super I/O | ITE IT8613E |
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+------------------+------------------------------+
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| SPI | Winbond W25Q128FV 16MiB 3.3V |
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+------------------+------------------------------+
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| NIC | Realtek RTL8111 |
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+------------------+------------------------------+
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| Audio | Realtek ALC897 |
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+------------------+------------------------------+
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```
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[Erying Polestar G613 Pro]: https://www.erying.cc/products-detail/id-97.html
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[microcodes]: https://github.com/platomav/CPUMicrocodes/tree/master/Intel
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[FSP XMP Flags]: https://github.com/intel/FSP/blob/master/TigerLakeFspBinPkg/Client/Include/FspmUpd.h#L586-L591
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[MrChromebox's EDK2]: https://github.com/MrChromebox/edk2
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[elly's EDK2]: https://github.com/ellyq/edk2
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[GOP driver]: https://github.com/MrChromebox/blobs/blob/master/soc/intel/tgl/IntelGopDriver.efi
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[flashrom]: https://flashrom.org/Flashrom
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[flashprog]: https://flashprog.org/wiki/Flashprog
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@ -97,6 +97,14 @@ QEMU x86 PC <emulation/qemu-i440fx.md>
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QEMU POWER9 <emulation/qemu-power9.md>
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```
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## Erying
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```{toctree}
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:maxdepth: 1
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Polestar G613 Pro <erying/tgl/tgl_matx.md>
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```
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## Facebook
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```{toctree}
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