mb/*: Drop xhci_overcurrent_mapping for the easy ones

This is now copied from USBOCM1 built with main USB port config.

Boards patched here have matching EHCI and xHCI overcurrent mappings.

Change-Id: I36944e2f2ed265ee492019b75b7dd8b95ca26dbb
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit is contained in:
Keith Hui 2025-01-09 11:48:51 -05:00 committed by Matt DeVillier
commit 8da3a048a8
28 changed files with 0 additions and 28 deletions

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@ -23,7 +23,6 @@ chip northbridge/intel/sandybridge
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x3f"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"

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@ -35,7 +35,6 @@ chip northbridge/intel/sandybridge
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x3f"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"

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@ -19,7 +19,6 @@ chip northbridge/intel/sandybridge
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "usb_port_config" = "{
{ 1, 0, 0 },

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@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
device ref xhci on end

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@ -44,7 +44,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx
# enable ONLY ports present on stock MintBox/Intense PC
#register "sata_port_map" = "0x1d"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"

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@ -29,7 +29,6 @@ chip northbridge/intel/sandybridge
device ref xhci on
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
end
device ref gbe off end

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@ -29,7 +29,6 @@ chip northbridge/intel/sandybridge
device ref xhci on
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
end
device ref sata1 on

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@ -29,7 +29,6 @@ chip northbridge/intel/sandybridge
device ref xhci on
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
end
end

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@ -28,7 +28,6 @@ chip northbridge/intel/sandybridge
}"
device ref xhci on
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
end
end

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@ -29,7 +29,6 @@ chip northbridge/intel/sandybridge
device ref xhci on
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
end
end

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@ -2,7 +2,6 @@ chip northbridge/intel/sandybridge
device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
device ref mei1 off end
register "xhci_overcurrent_mapping" = "0x00000c03"
device ref pcie_rp2 on end
device ref pcie_rp3 on
device pci 00.0 on # PCI 1969:1091

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@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge
# 0x1: 2.5", 0x2: DVD, 0x4: mSATA
register "sata_port_map" = "0x7"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "usb_port_config" = "{
{ 1, 0, 0 },

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@ -8,7 +8,6 @@ chip northbridge/intel/sandybridge
register "sata_port_map" = "0x3f"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_switchable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x0000000f"
register "usb_port_config" = "{
{ 1, 0, 0 },
{ 1, 0, 0 },

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@ -8,7 +8,6 @@ chip northbridge/intel/sandybridge
register "sata_port_map" = "0xf"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_switchable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x0000000f"
register "usb_port_config" = "{
{ 1, 0, 0 },
{ 1, 0, 0 },

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@ -21,7 +21,6 @@ chip northbridge/intel/sandybridge
# HDD(0), ODD(1), mSATA(2), eSATA(4)
register "sata_port_map" = "0x3f"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "usb_port_config" = "{
{1, 1, 0}, /* SSP1: dock */

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@ -20,7 +20,6 @@ chip northbridge/intel/sandybridge
register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
register "sata_port_map" = "0x33"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "usb_port_config" = "{
{1, 1, 0},

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@ -21,7 +21,6 @@ chip northbridge/intel/sandybridge
# HDD(0), ODD(1), mSATA(2), eSATA(4)
register "sata_port_map" = "0x3f"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "usb_port_config" = "{
{ 1, 1, 0 },

View file

@ -22,7 +22,6 @@ chip northbridge/intel/sandybridge
register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
register "sata_port_map" = "0x1f"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "usb_port_config" = "{
{1, 1, 0}, /* Dock USB3.0 */

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@ -20,7 +20,6 @@ chip northbridge/intel/sandybridge
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "sata_port_map" = "0x3"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "usb_port_config" = "{
{1, 1, 0}, /* SSP1: dock */

View file

@ -20,7 +20,6 @@ chip northbridge/intel/sandybridge
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "sata_port_map" = "0x1"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "usb_port_config" = "{
{ 1, 1, 0 },

View file

@ -32,7 +32,6 @@ chip northbridge/intel/sandybridge
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x5"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "usb_port_config" = "{
{ 1, 1, 0 },

View file

@ -34,7 +34,6 @@ chip northbridge/intel/sandybridge
# Do not enable xHCI Port 4 since WWAN USB is EHCI-only
register "superspeed_capable_ports" = "0x7"
register "xhci_switchable_ports" = "0x7"
register "xhci_overcurrent_mapping" = "0x04000201"
register "usb_port_config" = "{
{ 1, 1, 0 },
{ 1, 1, 1 },

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@ -43,7 +43,6 @@ chip northbridge/intel/sandybridge
# Wire port 4 (wwan usb) to ehci for it lacks superspeed components
register "xhci_switchable_ports" = "0x7"
register "superspeed_capable_ports" = "0xf"
register "xhci_overcurrent_mapping" = "0x4000201"
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "true"

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@ -42,7 +42,6 @@ chip northbridge/intel/sandybridge
register "xhci_switchable_ports" = "0xf"
register "superspeed_capable_ports" = "0xf"
register "xhci_overcurrent_mapping" = "0x4000201"
register "usb_port_config" = "{
{0, 3, 0 }, /* P00 disconnected */
{1, 1, 1 }, /* P01 left or right */

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@ -44,7 +44,6 @@ chip northbridge/intel/sandybridge
# Do not enable xHCI Port 4 since WWAN USB is EHCI-only
register "xhci_switchable_ports" = "0x7"
register "superspeed_capable_ports" = "0x7"
register "xhci_overcurrent_mapping" = "0x4000201"
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "true"

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@ -53,7 +53,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "false"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
register "xhci_overcurrent_mapping" = "0x00080401"
register "xhci_switchable_ports" = "0x0f"
register "superspeed_capable_ports" = "0x0f"
register "usb_port_config" = "{

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@ -58,7 +58,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "false"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0f"
register "superspeed_capable_ports" = "0x0f"
register "usb_port_config" = "{

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@ -24,7 +24,6 @@ chip northbridge/intel/sandybridge
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "usb_port_config" = "{
{ 1, 0, 0 },