Retrieve the SKU ID for Rauru via CBI interface. If that failed
(or no data found), fall back to ADC channels for SKU ID.
TEST=Build pass, boot ok, log show:
SKU Code: 0x2
BUG=b:317009620
Change-Id: I49ba6f428f55d3aae1b84a4d5ce06bec765caece
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85666
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
We add storage_id() to read the storage id from auxadc.
BUG=b:317009620
TEST=Build pass
Change-Id: I036df324cd6644ff69110c6247af29360b83225f
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85717
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add pujjo new supported memory parts in mem_parts_used.txt.
Generate SPD id for this part.
Hynix H58G56CK8BX146
BUG=b:385659484
TEST=Use part_id_gen to generate related settings
Change-Id: Idb48e849424aac79ef9af29f21b84194455c813e
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85735
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
These files were originally from MediaTek and follow coreboot's main
license: "GPL-2.0-only". Now MediaTek replaces this file to
"GPL-2.0-only OR MIT" license for better code re-use in other open
source software stack.
BUG=b:379008996
BRANCH=none
TEST=build pass
Change-Id: I2821a8c097b8d22e1aa91b316ae0fdce80f342de
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85723
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch enhances the readability of the CSE sync event
ELOG_TYPE_FW_CSE_SYNC by updating the event naming from "early and late
bootstage" to "pre and post memory."
BUG=b:379585294
TEST=boot verified on google/rex0 and google/rex64
without change:
```
rex-rev3 ~ # elogtool list
rex64-rev3 ~ # /media/usb/elogtool list
3 | 2024-01-01 22:25:59-0800 | Firmware CSE sync | Late CSE Sync
```
with change:
```
rex64-rev3 ~ # elogtool list
3 | 2024-12-17 02:22:36-0800 | Firmware CSE sync | Post RAM CSE Sync
```
Change-Id: Ia5db3ffb43b2ceac821de72ef9e88ed62e617d41
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Adjust the EC memory map range for indexed IO access in trulo variant
from 0x900 to 0x380
BUG=b:379224648
TEST= able to build nissa/trulo.
Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85547
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for indexed IO for ec communication, Indexed I/O allows
memory access using a single I/O port base address usually called an
index register and another port address called a data register.
BUG=b:379224648
TEST= able to build nissa/trulo.
Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch creates a new quandiso2 variant which is a Twin Lake
platform. This variant uses Quandiso board mounted with the Twin Lake
SOC and hence the plan is to reuse the existing quandiso code.
BRANCH=firmware-nissa-15217.B
TEST=build, and boot into OS
Change-Id: I404b579f1758c637d3456f6bed7119e3f4ecc06c
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85570
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Depending on the environment, the /data-in directory might be owned by
root and recent git versions refuse to work in these. So explicitly
mark /data-in as a safe environment.
Change-Id: Ia534928f759e50c2dfb1df8af653dee74c734603
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
There is no reason to stick to the point releases. So use the 3.19 base
image referring to the latest minor release instead. Also, update
installed packages to latest versions from that release.
Change-Id: Ic947f99ae7231918ec2e6105f8f3050a17fd1176
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
It seems the .bashrc is not loaded as intended and thus the bash
mechanisms never worked. So drop the bash invocations and replace them
with the ash shell. Also, don't modify the PATH variable since this is
done by the activation script.
Change-Id: I544a15c86c212e91ece59b583fb61dad37fca337
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Volumes are mounted with the command line parameter. Using the VOLUME
directive creates a persistent storage in a standard path, which is not
intended. So drop that and create equal directories in order to keep the
container working.
Change-Id: I9b3551cca34d846aba5ca5c89162f82baa6de768
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85724
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add watchdog support for MT8189.
BUG=b:379008996
BRANCH=none
TEST=build pass and WDT makes DUT reboot when MTK_WDT_MODE_ENABLE is
set.
Change-Id: I496fce91e52393db31fd1fb5a1c68d91b2ed073e
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85678
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Starting from MT8196, MediaTek platform introudces a new blob named
MediaTek firmware support package (mtk-fsp). The features of mtk-fsp
include but not limit to,
- Security settings, e.g: Device Access Proctection Control, Security
Memory Protection Unit.
- Initialization for advanced CPU frequency control.
This patch implements APIs for
1) Exchanging data between coreboot and mtk-fsp.
2) Loading and running the mtk-fsp blob at a specific bootstage.
BUG=b:373797027
TEST=emerge-rauru coreboot; Run mock blob and return from mock blob.
Change-Id: Idef3518f9763fe5f74adb459c137db164563e483
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85665
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update timer macro name for common.
The new ICs (e.g. mt8196, mt8189) will no longer use GPT. In order
to improve code readability, replace GPT_MHZ with TIMER_MHZ for
existing SoCs.
BUG=b:379008996
BRANCH=none
TEST=Build pass, Macro name is correct.
Change-Id: I02f18bfa5b5912f28e322d40cd46823a0095bbf4
Signed-off-by: Ke Zheng <ot_ke.zheng@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85681
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support for loading SPM firmware from CBFS to SPM SRAM
and fix the SPM register definitions. SPM needs its own firmware to
enable SPM suspend/resume function which turns off several resources
such as DRAM/mainpll/26M clk when linux system suspends.
coreboot log:
CBFS: Found 'spm_firmware.pm' @0xadf00 size 0x5a60 in mcache @0xfffdd3c
mtk_init_mcu: Loaded (and reset) spm_firmware.pm in 3 msecs (30080 byt)
TEST=build pass
BUG=348147674
Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e
Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85599
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename GSPI2 to GSPI0A to align with the latest Intel documentation
and platform specifications (doc: 815002)
BUG=b:377595986
TEST=Able to see 0x12.6 device is visible using `lspci`.
Change-Id: I9b87d38e44c07a053104b53df38ee1ce14a86c7f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
This change adds the ACPI name "SPI2" for the GSPI2 device
in the Panther Lake SOC.
Replace space with tab for PCI_DEVFN_GSPI2 macro.
w/o this patch:
[ERROR] Missing ACPI Name for PCI: 00:12.6
[ERROR] Missing ACPI Name for PCI: 00:12.6
w/ this patch:
No error
Change-Id: I404ddb893b82836e06d0f52a6d6f2aff2273d8c6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85712
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This to upgrade iasl from 20230628 to 20241212.
Change-Id: I4ae7073e46084024360ac0dd44e0df666cb32269
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Updating from commit id f1f70f46dc54:
2024-07-31 14:57:49 +0000 - (2lib: Add gbb flag to enforce CSE sync)
to commit id 3f94e2c7ed58:
2024-12-18 16:14:28 -0800 - (Makefile: Allow cross-compilation for RISC-V)
This brings in 49 new commits:
3f94e2c7ed58 Makefile: Allow cross-compilation for RISC-V
44c19d1893aa futility/updater: Remove obsolete write protection help URL
d1813a4666d7 futility: Add shell-parseable manifest format
2935820d404e vboot.rc: Mount tmpfs with SELinux context
c57a588f8029 crossystem: Change cros_debug to rely on mainfw_type, not devsw_boot
3ff18c08ee7d Android.bp: Remove host_supported for crossystem
dfd2b7c7404e Android.bp: Remove unused static libraries for firmware builds
f8eb37d14935 Makefile: Drop vboot_fw.a dependency for futility
0d49b8fdf002 recovery_kernel: add signing type recovery_kernel
1f7ca823da09 gpt_misc: Return uint64_t from GptGetEntrySize functions
3662103165a3 Reland "host/lib/flashrom: Use flashrom provided in PATH"
26e8011fd517 Add configurable temporary directory path
a0f83f9f3a0c futility: Drop futility execution logging to /tmp/futility.log
862e250e672c crossystem: Make crossystem vendor_available
3246e484ca08 futility: updater: Increase try count from 11 to 13
2ab8888bddac make_dev_ssd: add upstream cmdline flag for ptracers
3c2ef9400c05 Update Rust OWNERS file to include libchromeos-rs/OWNERS
c5af1fd8490d make_dev_ssd.sh: avoid page cache aliasing
38f9c255d31d Revert "host/lib/flashrom: Use flashrom provided in PATH"
7d4b23f9a054 futility: updater: Revise the test script
8494502d9f0b futility: updater: Support emulation in the output mode
54be900d8e1a futility: updater: Handle flashrom read failure in load_system_firmware
2a78755815d6 futility: updater: Drop `signature_id` from implementation
90f591700475 futility: updater: Add a new config 'output_only'
94d884d8a5bb futility: updater: Deprecate `--signature_id` by `--model`
24fd715c90e8 host/lib/flashrom: Use flashrom provided in PATH
ac49f1ca939b Build thin archives
640fe19f5f92 host/lib/crossystem: Make CROSSYSTEM_LOCK_PATH configurable
86b42b6a930c sign_android_image: calculate and store the vb meta digest
da1d153b4eed Move futility and cgpt to vendor partition
80955816aee0 futility: updater: Remove 'allow_empty_custom_label_tag' quirk
7ad2b0ab5035 futility: updater: Process custom label as standard models
13400d696a5e futility: updater: Remove signature_id from manifest
f770c7d074a2 futility: updater: Remove the legacy 'setvars.sh' manifest
ed4556edb968 tests/futility: Add test cases for unmodified RO
219026290256 futility/file_type_bios.c: Skip keyblock checks if magic is invalid
f5924321909d Fix partition type check for miniOS B
83f845b3b5da signing: clean up owners
dc5102f2f061 signing: miniOS signing in docker.
16e6aa8907fc futility: updater: Provide default DUT properties for emulation
e56f3686526c tests/futility/test_update: Fix --sys_props argument
7e2828a1bacf futility: updater: cleanup: Remove duplicated comments
060efa0cf64d vboot: Only execute TPM clear on nonchrome FW
2fc6815bf6b5 sign_official_build: Include full loem.ini path
47658f3c89e2 2lib/2load_kernel: Remove unused VB2_LOAD_PARTITION_WORKBUF_BYTES
7cc2ce4c902b futility: Skip printing EC RW version if non-printable
8365d546ce06 futility/load_fmap: Erase remaining bytes if file smaller than area
ec01126c04cd swap_ec_rw: Search for keyset in source tree too
b76d74dc08ac futility/load_fmap: use WARN() on non-critical error
Change-Id: I48f960235088c17dc59235b07926acd52e03deb2
Signed-off-by: Carlos López <carlos.lopez@openchip.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85676
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows building coreboot with AddressSanitizer on ChromeOS.
Otherwise these memory leaks are detected which cause the build to fail.
Change-Id: Ife6114db99278c9a3fb8271410486b057ef822f6
Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Configure GPP_F15 to generate an IRQ, that is used by the Virtual
Button driver to report whether the tablet is docked or undocked to
the OS.
Change-Id: I0815da09bd7ffd3926622e10df6a06ab5593dc2d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
This patch adds support for the Intel Virtual Button driver, which
reports whether a tablet is docked or undocked. The GPIO used for
detection is hardcoded to GPP_F15 for now, specific to the
`mb/starlite_adl` board.
The GPIO value is returned to the HID driver via the `_STA` and
`VGBS` methods. These methods ensure proper notification to the OS,
allowing it to show or hide the virtual keyboard depending on the
docking status.
Tested on `starlite_adl` with Ubuntu 24.04, confirming the virtual
keyboard appears when the tablet is undocked and hides when docked.
This was verified with ACPI debug enabled, as dmesg does not
report the state of the GPIO.
Change-Id: I574a1b2d3907b2341a0dfdc412151d574ba4848e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83879
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also drop the 24.11 release notes template.
Change-Id: Ifeb88a1bb4f05183ac9274de9b26970b6155017d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
touchpanel
1. Reuse DB_A (now DB_A_HDMI_LTE) as the HDMI switch.
2. Turn off the Type-C port C1 when using HDMI because both of them use
the same interface in hardware.
3. Use TOUCH_PANEL_I2C_GENERIC (formerly TOUCH_PANEL_DISABLE) to
support other screen models as we cannot have different fields to
support individual touch screen models.
BUG=b:365445053
TEST=emerge-nissa coreboot and run in DUT
Change-Id: I1900658f7c2e09180287a4e61f02e04be203b6e9
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85512
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Uldrenite supports the WWAN 5G device and uses variant.c to handle the
power-on sequence according to the Rolling Wireless_RW350R-GL_Hardware
Guide_Generic_V1.1. Due to no hardware access, the boot time is
estimated to increase by 50 ms.
At this stage, we do not yet have the board or key parts for
verification. However, I still need to merge the CL to ensure that the
WWAN functionality works. Once the motherboard is available, I will make
adjustments to optimize and reduce the boot time.
BUG=b:381393809, b:383212261
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Per Fabian Groffen <grobian@gentoo.org> in CB:75145:
This particular setting results in
[ERROR] PNP: 002e.308 missing read_resources
The underlying root cause was fixed by commit f5b993de4f
(sio/nuvoton/nct6779d: Correct GPIOBASE virtual LDN). However, to make
GPIO by I/O work requires setting up an I/O port resource here and
a generic LPC I/O decode at southbridge/intel/bd82x6x, and both weren't
done. Even if done, this newfound capability still doesn't offer much.
Change-Id: I39739ab71bc644619667b3e123cc9ad85f9d109f
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
According to Intel mFIT tool, SATA Port 0 is mapped as RP11 (PCI-E).
Disable SATA mapping on that port.
Setting SATAXPCIE1 GPIO fixes broken SATA port.
Therefore, this port is now fully functional.
TEST: Plug in 2.5in SATA drive, check detection in EDK2/Linux.
Change-Id: I9556383952d163a145ac73cb846740a4ce67a1e1
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85609
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Revert super I/O IRQ polarity settings replicated from OEM firmware
back to its power-on defaults.
With OEM settings COM 1/UART A/serial port 1 gets blocked right after
the kernel boots. It no longer works or responds, which actually means
the Linux boot process gets stuck forever when configured to write
to ttyS0.
Also revised the comment on another SIO setting to say it's being set
for PECI.
TEST=Not using these settings, I have not found any downside.
Serial keeps working, sensors still work, S3 suspend/resume works
correctly.
Reported by Fabian and confirmed by Keith.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Signed-off-by: Keith Hui <buurin@gmail.com>
Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
If CSE is in RO, then a reset is expected for CSE to jump to RW. Include
that reset in mainboard_expects_another_reset() logic. This will avoid
unnecessary warm reset during regular boot flow in boards with non-UFS
storage.
BUG=None
TEST=Build Brox BIOS image and boot to OS. Ensure that redundant reset
to disable UFS controller is avoided.
Before this change:
[INFO ] Disabling UFS controllers
[INFO ] Warm Reset after disabling UFS controllers
[INFO ] system_reset() called!
<snip>
[DEBUG] HECI: Global Reset(Type:1) Command
<snip>
[INFO ] Disabling UFS controllers
[INFO ] Warm Reset after disabling UFS controllers
[INFO ] system_reset() called!
After this change:
[DEBUG] HECI: Global Reset(Type:1) Command
<snip>
[INFO ] Disabling UFS controllers
[INFO ] Warm Reset after disabling UFS controllers
[INFO ] system_reset() called!
Change-Id: I80a46b15813b6bdfa6c029c54590f4b7c2a6754b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
CSE Sync Early Sign of Life (ESOL) event is logged as soon as the CSE FW
update is complete. This happens irrespective of whether Early Sign of
Life screen is enabled or not. Move CSE Sync ESOL event right before
displaying the ESOL screen.
BUG=b:378458829, b:379585294
TEST=Build Brox BIOS image and boot to OS. Ensure that the ESOL event
for CSE Sync is logged.
Change-Id: Iaa0dbb87ddde69dc3f4a9e058fc6bed8711b29e7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85111
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
According to the discussion on the issue tracker, set
GPP_A14 as USB_OC1 for the A0 port
BUG=b:380789023
TEST=emerge-nissa coreboot
Change-Id: I2b782216c0392b1a98ea57300e683c32999d5a32
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
According to the discussion on the issue tracker, set GPP_B5
and GPP_B6 to the ISH function.
BUG=b:383696667
TEST=emerge-nissa coreboot
Change-Id: I0c98206edd89c90cb1c341a8f713f09f4b8bf0e7
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85601
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Add new folder and basic drivers for Mediatek SoC 'MT8189'.
Also enable UART and ARM arch timer.
This commit includes the necessary initialization files for MT8189,
which cannot be shared with other existing SoCs.
The modules included are:
- Memory layout: MT8189 has only 64KB of SRAM, differing in space
allocation compared to other SoCs.
- PLL: Different SoCs have different PLL designs. In this commit,
we provide the most basic settings, with more configurations to
be added in future commits.
- Timer: MT8189 uses timer v2, unlike other SoCs which use timer v1.
- SPI: The SPI driver for different SoCs varies depending on the GPIO/
PIN MUX used. In this commit, we provide the most basic settings,
with more configurations to be added in future commits.
- EMI: MT8189 uses common EMI code along with MT8189-specific
'dram_parameter.h'. This commit provides an EMI stub to ensure
coreboot builds successfully. Future DRAM-related commits will
utilize the common EMI code.
BUG=b:379008996
BRANCH=none
TEST=saw the coreboot uart log to bootblock
Change-Id: I5d83c4c7fba49e455fac0b58f019ad225f83c197
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85616
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MediaTek pwrsel (Power Select) is mainly used to reduce power
consumption, controlled by mcupm.
BUG=b:317009620
TEST=Build pass
Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This change allows the Chrome EC (CREC) ACPI device to publish the LPC
Generic Memory Range (GMR) address range using the _CRS method.
The Google CREC driver can now parse this information to determine the
MMIO address map, enabling access to the LPC GMR register space.
This addresses the issue where the CREC driver was unable to
automatically determine the LPC GMR base address.
TEST=Able to build and boot google/brox.
without this patch:
brox-rev0 ~ # cat /proc/iomem | grep fe0
fe000000-fe00ffff : INTC1026:00
fe000000-fe00ffff : intel_scu_ipc
fe03e000-fe03efff : 0000:00:1e.0
fe03e000-fe03e1ff : lpss_dev
fe03e000-fe03e1ff : serial
fe03e200-fe03e2ff : lpss_priv
fe03e800-fe03efff : idma64.4
fe03e800-fe03efff : idma64.4 idma64.4
with this patch:
brox-rev0 ~ # cat /proc/iomem | grep fe0
fe000000-fe00ffff : INTC1026:00
fe000000-fe00ffff : intel_scu_ipc
fe03e000-fe03efff : 0000:00:1e.0
fe03e000-fe03e1ff : lpss_dev
fe03e000-fe03e1ff : serial
fe03e200-fe03e2ff : lpss_priv
fe03e800-fe03efff : idma64.4
fe03e800-fe03efff : idma64.4 idma64.4
fe0b0000-fe0bffff : GOOG0004:00
Change-Id: Ib3ea3e2a482f9eceaa8c15e38b7e708b156bc978
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85603
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
