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mb/topton/adl: Disable mapped SATA port

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According to Intel mFIT tool, SATA Port 0 is mapped as RP11 (PCI-E).
Disable SATA mapping on that port.

Setting SATAXPCIE1 GPIO fixes broken SATA port.
Therefore, this port is now fully functional.

TEST: Plug in 2.5in SATA drive, check detection in EDK2/Linux.

Change-Id: I9556383952d163a145ac73cb846740a4ce67a1e1
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85609
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Alicja Michalska 2024-12-16 21:50:52 +01:00 • committed by Felix Singer
commit 4f1a1adef6
2 changed files with 1 additions and 4 deletions
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3
src/mainboard/topton/adl/devicetree.cb
View file

@ -42,11 +42,8 @@ chip soc/intel/alderlake
end
device ref shared_sram on end
# Not working, resource conflict(?)
device ref sata on
register "sata_ports_enable" = "{
[0] = 1,
[1] = 1,
}"
end

2
src/mainboard/topton/adl/gpio.h
View file

@ -68,7 +68,7 @@ static const struct pad_config gpio_table[] = {
_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), /* ESPI_CLK */
_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* ESPI_RESET# */
PAD_CFG_GPO(GPP_A11, 1, PLTRST), /* GPIO */
PAD_NC(GPP_A12, NONE), /* GPIO */
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), /* SATAXPCIE1 */
PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPIO */
_PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* USB_OC1# */
_PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */