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mb/trulo/var/uldrenite: Support USB_OC on the A0 port

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According to the discussion on the issue tracker, set
GPP_A14 as USB_OC1 for the A0 port

BUG=b:380789023
TEST=emerge-nissa coreboot

Change-Id: I2b782216c0392b1a98ea57300e683c32999d5a32
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
This commit is contained in:
John Su 2024-12-18 17:29:17 +08:00 • committed by Subrata Banik
commit c812c78618
2 changed files with 3 additions and 3 deletions
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4
src/mainboard/google/brya/variants/uldrenite/gpio.c
View file

@ -30,8 +30,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_A12, NONE),
/* A13 : GPP_A13 ==> SOC_BT_ON */
PAD_CFG_GPO_LOCK(GPP_A13, 1, LOCK_CONFIG),
/* A14 : USB_OC1# ==> NC */
PAD_NC(GPP_A14, NONE),
/* A14 : USB_OC1# */
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* A15 : USB_OC2# ==> NC */
PAD_NC(GPP_A15, NONE),
/* A16 : USB_OC3# ==> NC */

2
src/mainboard/google/brya/variants/uldrenite/overridetree.cb
View file

@ -63,7 +63,7 @@ chip soc/intel/alderlake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB2_A0
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # User Facing Camera
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # World Facing Camera