mb/google/skywalker: Add MediaTek MT8189 reference board

Add mainboard folder and drivers for new reference board 'Skywalker'.

BUG=b:379008996
BRANCH=none
TEST=saw the coreboot uart log to bootblock

Change-Id: I690508fea91c790f202f234f89be8f3cf4d09546
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85617
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/skywalker/Kconfig

@@ -0,0 +1,30 @@
+## SPDX-License-Identifier: GPL-2.0-only OR MIT
+
+# Umbrella option to be selected by variant boards.
+config BOARD_GOOGLE_SKYWALKER_COMMON
+	def_bool BOARD_GOOGLE_SKYWALKER
+
+if BOARD_GOOGLE_SKYWALKER_COMMON
+
+config VBOOT
+	select VBOOT_VBNV_FLASH
+	select VBOOT_NO_BOARD_SUPPORT
+	select VBOOT_MOCK_SECDATA
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SOC_MEDIATEK_MT8189
+	select BOARD_ROMSIZE_KB_8192
+	select MAINBOARD_HAS_CHROMEOS
+	select COMMON_CBFS_SPI_WRAPPER
+	select SPI_FLASH
+	select SPI_FLASH_INCLUDE_ALL_DRIVERS
+
+config MAINBOARD_DIR
+	string
+	default "google/skywalker"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Skywalker" if BOARD_GOOGLE_SKYWALKER
+endif

src/mainboard/google/skywalker/Kconfig.name

@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only OR MIT
+
+comment "Skywalker"
+
+config BOARD_GOOGLE_SKYWALKER
+	bool "->  Skywalker"

src/mainboard/google/skywalker/Makefile.mk

@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only OR MIT
+
+all-y += memlayout.ld
+all-y += chromeos.c
+all-y += reset.c
+
+bootblock-y += bootblock.c
+
+romstage-y += romstage.c
+
+ramstage-y += mainboard.c

src/mainboard/google/skywalker/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Skywalker MediaTek MT8189 reference board
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/google/skywalker/bootblock.c

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <bootblock_common.h>
+
+void bootblock_mainboard_init(void)
+{
+	/* TODO: add mainboard init for bootblock */
+}

src/mainboard/google/skywalker/chromeos.c

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	/* TODO: add ChromeOS specific gpios */
+}

src/mainboard/google/skywalker/chromeos.fmd

@@ -0,0 +1,46 @@
+# Firmware Layout Description for ChromeOS.
+#
+# The size and address of every section must be aligned to at least 4K, except:
+# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.
+#
+# 'FMAP' may be found by binary search so its starting address should be better
+# aligned to larger values.
+#
+# For sections to be preserved on update, add (PRESERVE) to individual sections
+# instead of a group section; otherwise the preserved data may be wrong if you
+# resize or reorder sections inside a group.
+
+FLASH@0x0 8M {
+	WP_RO@0x0 4M {
+		RO_SECTION {
+			BOOTBLOCK 128K
+			FMAP 4K
+			COREBOOT(CBFS)
+			GBB 0x2f00
+			RO_FRID 0x100
+		}
+		RO_GSCVD 8K
+		RO_VPD(PRESERVE) 32K  # At least 16K.
+	}
+	RW_SECTION_A 1500K {
+		VBLOCK_A 8K
+		FW_MAIN_A(CBFS)
+		RW_FWID_A 0x100
+	}
+	RW_MISC 36K {
+		RW_VPD(PRESERVE) 16K  # At least 8K.
+		RW_NVRAM(PRESERVE) 8K
+		RW_MRC_CACHE(PRESERVE) 8K
+		RW_ELOG(PRESERVE) 4K  # ELOG driver hard-coded size in 4K.
+	}
+	RW_SECTION_B 1500K {
+		VBLOCK_B 8K
+		FW_MAIN_B(CBFS)
+		RW_FWID_B 0x100
+	}
+	RW_SHARED 36K {  # Will be force updated on recovery.
+		SHARED_DATA 4K  # 4K or less for netboot params.
+		RW_UNUSED
+	}
+	RW_LEGACY(CBFS) 1M  # Minimal 1M.
+}

src/mainboard/google/skywalker/devicetree.cb

@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only OR MIT
+
+chip soc/mediatek/mt8189
+	device cpu_cluster 0 on end
+end

src/mainboard/google/skywalker/mainboard.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <device/device.h>
+
+static void mainboard_init(struct device *dev)
+{
+	/* TODO: add mainboard init */
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+	.name = CONFIG_MAINBOARD_PART_NUMBER,
+	.enable_dev = mainboard_enable,
+};

src/mainboard/google/skywalker/memlayout.ld

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <soc/memlayout.ld>

src/mainboard/google/skywalker/reset.c

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <reset.h>
+
+void do_board_reset(void)
+{
+	/* TODO: add reset function when gpio is ready */
+}

src/mainboard/google/skywalker/romstage.c

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <arch/stages.h>
+
+void platform_romstage_main(void)
+{
+	/* TODO: add romstage main function */
+}