mb/google/fatcat/var/fatcat: Enable FPS
Lists of changes: - GPIO programmimg when FW_CONFIG bit 17 is set FPMCU_PWREN -> GPP_E19 -> OUTPUT SOC_INT_L -> GPP_D1 -> INPUT FPMCU_FW_UPDATE -> GPP_E20 -> NF1 FPS_RST_N -> GPP_C15 -> OUTPUT GPP_F16_GSPI0A_CLK -> GPP_F16 -> SPI CLK -> NF8 GPP_F15_GSPI0A_MISO -> GPP_F15 -> SPI MISO -> NF8 GPP_F14_GPSI0A_MOSI -> GPP_F14 -> SPI MOSI -> NF8 GPP_F18_GSPI0A_CS0 -> GPP_F18 -> SPI CS -> NF8 - GPIO programmimg when FW_CONFIG bit 17 is not set GPP_E19 -> NC MOD_TCSS1_TYP_A_VBUS_EN -> GPP_D1 -> OUTPUT GPP_E20 -> NC GPP_C15 -> NC GPP_F16 -> NC GPP_F15 -> NC GPP_F14 -> NC GPP_F18 -> NC - ACPI Entry - Keep ISH (0x12.0) enable for GSPI0A to be operational - Keep GSPI0/1 disable and GSPI0A enable (PCI) BUG=b:377595986 TEST=TBD Change-Id: Ifced5c779407b4ffcc69a7ed1297704def09b554 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Subrata Banik
parent
acb8c870b2
commit
639def1d84
3 changed files with 70 additions and 16 deletions
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@ -474,6 +474,42 @@ static const struct pad_config ish_enable_pads[] = {
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PAD_CFG_NF(GPP_F23, NONE, DEEP, NF8),
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};
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static const struct pad_config fp_disable_pads[] = {
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PAD_NC(GPP_C15, NONE),
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/* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */
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PAD_CFG_GPO(GPP_D01, 1, DEEP),
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PAD_NC(GPP_E19, NONE),
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PAD_NC(GPP_E20, NONE),
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PAD_NC(GPP_F14, NONE),
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PAD_NC(GPP_F15, NONE),
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PAD_NC(GPP_F16, NONE),
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PAD_NC(GPP_F18, NONE),
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};
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static const struct pad_config fp_enable_pads[] = {
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/* GPP_C15: FPS_RST_N */
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PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
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/* GPP_D01: FPS_SOC_INT_L */
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PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT),
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/* GPP_E19: FPMCU_PWREN */
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PAD_CFG_GPO(GPP_E19, 1, DEEP),
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/* GPP_E20: FPMCU_FW_UPDATE */
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PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
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/* GPP_F14: GPSI0A_MOSI */
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PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
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/* GPP_F15: GSPI0A_MISO */
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PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
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/* GPP_F16: GPSI0A_CLK */
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PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
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/* GPP_F18: GSPI0A_CS0 */
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PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
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};
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static const struct pad_config pre_mem_fp_enable_pads[] = {
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/* GPP_C15: FPS_RST_N */
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PAD_CFG_GPO(GPP_C15, 0, DEEP),
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};
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void fw_config_configure_pre_mem_gpio(void)
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{
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if (!fw_config_is_provisioned()) {
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@ -517,6 +553,10 @@ void fw_config_configure_pre_mem_gpio(void)
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*/
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if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT)))
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GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq2_pads);
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if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
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GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads);
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}
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void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
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@ -607,4 +647,9 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
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/* NOTE: disable PEG (x8 slot) and x4 slot wake for now */
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GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads);
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if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
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GPIO_CONFIGURE_PADS(fp_enable_pads);
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else
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GPIO_CONFIGURE_PADS(fp_disable_pads);
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}
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@ -130,8 +130,6 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
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/* GPP_C14: CLKREQ5_X1_GEN4_M2_WWAN_N */
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PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
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/* GPP_C15: CRD1_CLK_EN */
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PAD_CFG_GPO(GPP_C15, 1, PLTRST),
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/* GPP_C16: TBT_LSX0_TXD */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/* GPP_C17: TBT_LSX0_RXD */
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@ -151,8 +149,6 @@ static const struct pad_config gpio_table[] = {
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/* GPP_D00: IMGCLKOUT_1 */
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PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
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/* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */
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PAD_CFG_GPO(GPP_D01, 1, DEEP),
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/* GPP_D02: Not used */
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PAD_NC(GPP_D02, NONE),
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/* GPP_D03: M.2_WWAN_PERST_GPIO_N */
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@ -234,10 +230,6 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
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/* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */
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PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
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/* GPP_E19: PEG_SLOT_DGPU_SEL_N */
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PAD_CFG_GPO(GPP_E19, 1, PLTRST),
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/* GPP_E20: PEG_SLOT_DGPU_PWR_OK */
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PAD_CFG_GPI(GPP_E20, NONE, PLTRST),
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/* GPP_E21: I2C_PMC_PD_INT_N */
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PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
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/* GPP_E22: THC0_SPI1_DSYNC */
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@ -277,16 +269,8 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
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/* GPP_F13: THC_I2C1_SDA_TCH_PAD */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
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/* GPP_F14: Not used */
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PAD_NC(GPP_F14, NONE),
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/* GPP_F15: Not used */
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PAD_NC(GPP_F15, NONE),
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/* GPP_F16: Not used */
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PAD_NC(GPP_F16, NONE),
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/* GPP_F17: Not used */
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PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
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/* GPP_F18: TCH_PAD_INT_N */
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PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
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/* GPP_F19: GPP_PRIVACY_LED_CAM2 */
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PAD_CFG_GPO(GPP_F19, 0, PLTRST),
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/* GPP_F20: GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */
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@ -107,6 +107,12 @@ chip soc/intel/pantherlake
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "serial_io_gspi_mode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI0A] = PchSerialIoPci,
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}"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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@ -357,12 +363,31 @@ chip soc/intel/pantherlake
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device ref ish on
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probe ISH ISH_ENABLE
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probe FP FP_PRESENT
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chip drivers/intel/ish
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register "add_acpi_dma_property" = "true"
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device generic 0 on end
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end
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end
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device ref gspi0a on
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chip drivers/spi/acpi
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register "name" = ""CRFP""
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "uid" = "1"
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register "compat_string" = ""google,cros-ec-spi""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)"
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register "wake" = "GPE0_DW1_01"
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register "has_power_resource" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
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register "enable_delay_ms" = "3"
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device spi 0 on
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probe FP FP_PRESENT
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end
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end # FPMCU
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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