mb/google/brox: Include CSE reset in mainboard reset expectation
If CSE is in RO, then a reset is expected for CSE to jump to RW. Include that reset in mainboard_expects_another_reset() logic. This will avoid unnecessary warm reset during regular boot flow in boards with non-UFS storage. BUG=None TEST=Build Brox BIOS image and boot to OS. Ensure that redundant reset to disable UFS controller is avoided. Before this change: [INFO ] Disabling UFS controllers [INFO ] Warm Reset after disabling UFS controllers [INFO ] system_reset() called! <snip> [DEBUG] HECI: Global Reset(Type:1) Command <snip> [INFO ] Disabling UFS controllers [INFO ] Warm Reset after disabling UFS controllers [INFO ] system_reset() called! After this change: [DEBUG] HECI: Global Reset(Type:1) Command <snip> [INFO ] Disabling UFS controllers [INFO ] Warm Reset after disabling UFS controllers [INFO ] system_reset() called! Change-Id: I80a46b15813b6bdfa6c029c54590f4b7c2a6754b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
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@ -3,6 +3,7 @@
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#include <baseboard/variants.h>
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#include <cbfs.h>
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#include <ec/google/chromeec/ec.h>
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#include <intelblocks/cse.h>
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#include <security/vboot/vboot_common.h>
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#include <security/vboot/misc.h>
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#include <soc/romstage.h>
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@ -53,9 +54,14 @@ static bool check_auxfw_ver_mismatch(void)
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bool mainboard_expects_another_reset(void)
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{
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/* Do not change the order of the check in this function */
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if (vboot_recovery_mode_enabled())
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return false;
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/* If CSE is booting from RO, CSE state switch will issue a reset anyway. */
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if (!is_cse_boot_to_rw())
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return true;
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if (!CONFIG(VBOOT) ||
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(vboot_is_gbb_flag_set(VB2_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC) &&
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vboot_is_gbb_flag_set(VB2_GBB_FLAG_DISABLE_AUXFW_SOFTWARE_SYNC)))
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