Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to 1 in the moonstone variant
overridetree. This ensures the display engine operates at the required
frequency (442Mhz) for the panel to meet the hardware configuration.
BUG=b:484559627
TEST=Build and boot google/moonstone, verify display initialization.
Change-Id: I4d3d0082f9f221333150bd5b427b3f20e7a2f154
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91236
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the ptlrvp
baseboard devicetree. This ensures the display engine operates at
the required frequency for the panel to meet the hardware configuration.
BUG=b:458353982
TEST=Build and boot ptlrvp, verify display initialization.
Change-Id: I34abb742ab5d95da4d21ea22da2b1bc7270f1a9c
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the fatcat
baseboard devicetree. This ensures the display engine operates at the
required frequency for the panel to meet the hardware configuration.
BUG=b:458353982
TEST=Build and boot fatcat/lapis, verify display initialization.
Change-Id: If8812bc66149b402adb7b9159f3a28d35903b785
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add/update FP enable/disable based on SKU ID. This is meant
to resolve a UMA issue with devices that had the FPMCU populated on
non-fp devices. Since the FPMCU is present, and the firmware enables
the power GPIO's based on variant, not SKU, the devices were reporting
data on fingerprint errantly. Specify the SKUs which should not have a
FP sensor and default to true to maintain the legacy behavior for
undefined devices and limit risk. Variants which do not have FP SKUs
will be unaffected.
BUG=b:354769653,b:484162286
TEST=Flash on device, test FP.
Disable test SKU, flash on device, test FP.
To test, run `ectool --name=cros_fp version` in the shell
When enabled, the fpmcu fw version should be displayed.
When disabled, an error should be displayed because the fpmcu
is inaccessible.
Change-Id: I6998534e3b9c5909839aceb886ab04a04f394289
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91329
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Verify that a battery is actually present before setting the boot
mode to LB_BOOT_MODE_OFFMODE_CHARGING. This prevents the system
from incorrectly entering a charging state when running on AC power
without a battery connected.
TEST=Build and boot on bluey with and without battery present.
Verify boot mode transitions correctly.
Change-Id: I67098bc06b34c25429daf516f3891c50930209fe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
- Drop USB OC2#, OC3#, OC4#, OC6#
Those are either pulled high or used as GPIO and used by internal
devices only.
- Disable Port 4, 6, 7. They are unused.
- Add comments with devices connected.
TEST=On Lenovo x220 the USB ports P00, P01, P02, P03, P08, P09, P11,
P13 are still working.
Change-Id: I00b0a36a80b812adb9a4ee976dabb528afd36409
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91233
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow the user to disable PCIe ports that are not required.
Change-Id: Id2d7640255c347c768387408f27e9f5448cbef01
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Automatically use the CFR driver when EDK2 payload and SMMSTORE
are enabled. Selects the UEFI variable option backend by default
when SMMSTORE is enabled.
Change-Id: Ib7cb122dc863d3449c670d1917ebdd2a0a6317d0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Address x1 slot enumeration issues for certain add in cards (AICs)
during boot. This change implements proper power sequencing and adds
support for AICs that use PRSNT2# signaling instead of ClkReq#. The
x1 slot power rail (X1_PCIE_SLOT_PWR_EN via GPP_A8) is pull-high by
design, with GPP_A08 PAD defaulting to GPI configuration. This enables
slot power during early boot phases. PERST# (GPP_D19) is logically
ANDed with PLTRST#, ensuring PLTRST# de-assertion occurs only after x1
slot power stabilization, maintaining proper PCIe timing automatically.
For scenarios requiring power-off at boot, the following sequence
ensures compliance with PCIe link training timing requirements:
Step 1 (romstage): ClkReq PAD off; PERST# asserted; power off
Step 2 (ramstage at BS_PRE_DEVICE exit): Power on; ClkReq PAD on (if
used)
Step 3 (ramstage at BS_DEV_INIT_CHIPS entry): PERST# de-asserted
The CBI fw_config SD field has been redefined to accommodate different
AIC types:
- SD_BAYHUB: For AICs supporting ClkReq# signaling
- SD_GENSYS: For AICs using only PRSNT2# signaling
BUG=None
TEST=Boot Fatcat board with AIC cards configured via CBI fw_config SD
field (SD_BAYHUB or SD_GENSYS). Confirm PCIe device enumeration
appears correctly in boot log. For instance:
[SPEW ] do_pci_scan_bridge for PCI: 00:00:1c.0
[DEBUG] PCI: pci_scan_bus for segment group 00 bus ae
[DEBUG] PCI: 00:ae:00.0 [1217/9860] enabled
The device should be seen from lspci command, such as:
ae:00.0 Class 0805: Device 1217:9860 (rev 01)
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I94a7ee2ecd8d3fd83006297ef68f97ff49e47595
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90000
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move Gen4 SSD power enable (GPP_B10) from ramstage GPIO table to
pre-memory configuration to ensure proper delay between power enable
and reset signals. This is required to fix PCIe speed downgrade or
link failure issues seen with some NVMe parts when a non-serial image
is used for boot.
Changes:
- Enable GPP_B10 (GEN4_SSD_PWREN) in pre_mem_gen4_ssd_pwr_pads
- Remove duplicate GPP_B10 configuration from gen4_ssd_pads
- Remove GPP_B10 from ramstage gpio_table
BUG=None
TEST=Boot to OS, check PCIe link speed for SSD.
Change-Id: I969a0d5576b9a229f70a4d01737b7f594876b106
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90523
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select the discrete TBT controller driver, and configure the necessary
GPIOs for the Alpine Ridge TBT controller to be fully functional.
Add ACPI to ensure the TBT controller properly handles S3 sleep and
resume. Update the documentation w/r/t TBT functionality.
TEST=build/boot Lenovo T480, boot Linux, verify all TBT-related PCI
devices populated, lower USB-C port works for USB data and PCIe.
Change-Id: Ie5586fa72ed6819b9d1c37373c21605d39bad7b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88490
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The HX boards, using PCH-S, use a discrete Thunderbolt device (Intel
Maple Ridge), as opposed to a built-in one like the boards using PCH-P.
Fixes Thunderbolt on RPL-HX boards using the Maple Ridge controller.
Change-Id: I53d18f3ec5a084431e1113782c791bcb42728350
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76584
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evie (Ivi) Ballou <iviballou@gmail.com>
The mc_ehl8 variant has an RTC (RV3028-C7) at SMBus address 0x52, which
falls within the SPD EEPROM address range (0x50-0x57). By default, FSP
write-protects this range.
Disable write protection for mc_ehl8 to allow RTC configuration.
TEST=Boot system into OS and use i2ctools to read out registers
0x00-0x06 of the RTC to verify that the driver set the correct date
and time.
Change-Id: I0e6426f57d7e316a74102b1e5352ce9d334eac02
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91200
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Windows 11 ACP driver depends on the ACPI _DSD method, thus
add the data based on the UEFI implementation.
TEST=Windows 11 ACP driver reports no issues any more.
Change-Id: I3e193ee0dbf736aab9f7d21927a01992e2f84973
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Eliminates errors in cbmem log:
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping
not found
Change-Id: I562e63365599a2dc62526f5789b7c6c79318cb9e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This board does not have a DMIC, so update the verb table to
reflect that.
Change-Id: Idd38dc016d7d178002f291ac8a0088e5f7b7490d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This fixes an integer overflow in the calculation of the offset within
the SPD binary that has caused memory detection failures on some
machines (e.g. this resolves https://ticket.coreboot.org/issues/627 ).
In a nutshell, spd_index (uint8_t) receives an assigned multiplication
by 512 (SPD_SIZE_MAX_DDR4) which will always truncate the result.
Change-Id: I048a73c18c9a3d1b20e2a4276e1714e59550eaf5
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91170
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Lapis project uses a USB camera and does not have
a MIPI camera, therefore the IPU interface is disabled.
BUG=b:475355637
TEST=emerge-fatcat coreboot
Change-Id: I35273251d73a3f885b7dd8750b746dbca06e9564
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91180
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMBus controller was previously disabled on the Lapis variant.
Enable the SMBus device in the overridetree to allow the system to
communicate with onboard peripherals like the SPD EEPROMs and
thermal sensors.
BUG=none
TEST=Build and boot on Lapis; verify smbus is initialized.
Change-Id: I9d7254b6c2686ec67392294d45b870e3670f2aca
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91196
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select HAVE_CHARGING_DEBUG_ACCESS_PORT for the Quartz variant.
BUG=b:474297115
TEST=Verified that quartz starts charging when the charger is connected
via the servov4.1 to the C0 port.
TEST=Verified that quartz starts charging when the charger is directly
connected to the C0 port.
TEST=Verified that the battery is charging by checking the battery
State of charge after 20-30 mins of charging.
Change-Id: Ie5e0d980780daa0adeee4e6a3e3525eb2616a29f
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
When the system is in a low-power boot state or early charging mode,
it is necessary to enable charging even when a debug access port
is connected. This ensures that developers can charge the
device while using the servov4.1 with the charger.
This patch updates the charging configuration to enable the debug
access sink by writing to the TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG
register.
BUG=b:474297115
TEST=Build Google/quartz
Change-Id: I155b071e678c8bc0ff0d719ac924b5026b21b37a
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91077
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This CL aims to make the code support ready before touchscreen launch.
BUG=b:483588481
TEST=build brox coreboot image
Change-Id: I9f8715311c976e92049ff3058920039c0d38ba3a
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
This CL aims to make the code support ready before touchscreen launch.
BUG=b:483762467
TEST=build nissa coreboot image
Change-Id: I919f92b782905ea9184203804f5ea095e37e9893
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add configuration for the PCIe Root Port connected to the WiFi 7 module.
BUG=b:481186489
TEST=Build successfully for moxoe. Verify WiFi 7 functionality on
moxie.
Change-Id: I8941b587ac35f6c03654de959cc93350b5604b35
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91103
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Update the logo_bottom_margin for all fatcat variants from 100px to
200px. This adjustment ensures the OEM footer logo and associated
splash text are rendered higher on the screen, improving visibility
and alignment with updated UX requirements.
Modified variants:
- fatcat
- felino
- francka
- kinmen
- lapis
- moonstone
- ruby
Change-Id: Ia0f446768f1b0b13c09873176f79ed4418f28aa2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91155
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure lapis to use coreboot (CHIPSET_LOCKDOWN_COREBOOT) to set BIOS
interface lock. Otherwise, FSP code will be responsible for locking the
chipset.
BUG=None
TEST=Able to build and boot lapis
Change-Id: Ia3a13390e4a1862164d820dd1ee220dea682a6a0
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
The Birman+ evaluation board allows to test different display
connectors (HDMI, Displayport, ...) by plugin in different "NOVA"
cards. Every NOVA card has a small EEPROM identifying the connector.
Currently the graphics init isn't working with a DisplayPort
monitor connected to the DP NOVA card.
Fix the auto-detection code of the NOVA card. The code was swapping
the endianness of the connector_type which isn't necessary according
to the spec, but it looks like some cards where programmed with
different endianness.
To support both types, little and big endian, accept both for now.
TEST=Can boot into EDK2 with graphics enabled.
Change-Id: I54754967dd4887363043808116495cb36c636baf
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Enable TCP0 alongside TCP1.
Test=build and boot adl/horizon, check there is video output over
USB-C.
Change-Id: I9db17fd3ed3e1eb0f6ea94320b595ce0d51f33e2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91168
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some of the entries were indexed wrong, so fix them.
Change-Id: I76890a3c3b2b30d8123a81352346776a656e8f7f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91167
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add configuration for the PCIe Root Port connected to the WiFi 7 module.
BUG=b:480035819
TEST=Build successfully for kulnex. Verify WiFi 7 functionality on
moxie.
Change-Id: I46dfe87afe7356cbe48cf15dd87a58b55a528094
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91071
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before the PCIe features can be programmed FSP-S must set non
public bits in the EnumInitPhaseAfterPciEnumeration callback.
Violating this rule causes system instabilities and reboot loops,
depending on the selected features and hardware plugged into slots.
Since FSP-S can handle all types of PCIe features disable all of
them in coreboot and let FSP set the bits at the right time.
TEST=Can boot on AMD/glinda with ASPM L1SS enabled without seeing
system crashed.
Change-Id: Ib4c4597c91d6612018e4f55e1a989a676aff842d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91164
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The default CPU for birman_plus is STX1FP8 with a TDP of 28W.
Set SystemConfig to 2 to use the default IRM configuration
for 28W TDP CPUs and tweak slow PPT and fast PPT.
Change-Id: I555326228ad6a1dfa2f18c7fbd5a69b9b95b0f04
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
A Windows driver bug resulted in the max98357a-tdm topology being
identified as the correct one, when in fact the non-TDM version is
correct. Now that the bug has been fixed, correct the speaker
topology. Linux was unaffacted as it uses a different mapping
method.
TEST=build/boot Win11 on RPL Taeko, verify audio functional out
of both left/right speakers and mixer functions properly.
Change-Id: I2f9cc7353540cd8722beada656a8c2a8b1ba8669
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91144
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the Sandybridge Lenovo devices are spending 25msec waiting
for ME to signal if RAM has been replaced. At the same time the RFID
I2C EEPROM needs to be locked, taking about 26msec.
By moving the locking to romstage the time spent waiting for ME can
be used to do something useful and thus reduce boot time.
TEST=On Lenovo X220 it boots 24msec faster.
Change-Id: Idd1f02a20dab6e422d55e3cf01d7b4a168792272
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Create the kulnex variant of the kuldax project by
copying the files to a new directory named for the variant.
BUG=b:480035819
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KULNEX
Change-Id: Ice06b67aeaa3bb8f36a6d3721014888defbfac15
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Create the moxoe variant of the moxie project by
copying the files to a new directory named for the variant.
BUG=b:481186489
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MOXOE
Change-Id: I5dd9cc21b647834144cfffcd43bdcf84e9df3a0c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
This commit adds a wake configuration to the cnvi_bluetooth device for
the ruby variant. The "wake" setting is now registered to "GPE0_PME_B0"
using the common CNVi block. This enhancement ensures that the
cnvi_bluetooth device can properly wake the system.
TEST=Able to wake up the device from a low power state using a keyboard
Bluetooth device.
Change-Id: If1b3af2a9ad8c3e3800f5c839190727d78122853
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
When disabling slow battery charging, explicitly set the Fast Charge
Current (FCC) configuration to 0x8c (disable) for both SMB1 and SMB2
controllers.
This ensures that the PMIC charging registers are returned to a
neutral/safe state while disabling the charging.
BUG=b:481546101
TEST=Build and boot Bluey. Verified that SMB1/SMB2_CHGR_MAX_FCC_CFG
registers are cleared during the disable_slow_battery_charging call.
Change-Id: Ic5da492b097747dec88b117ac021759644b8b816
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91121
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the juchi variant of the jubilant project by
copying the files to a new directory named for the variant.
BUG=b:481602501
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_JUCHI.
Change-Id: I4a1919f6a2480e4e2f993fa24658836a1739714c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Update fast_vmode_i_trip array references as per 813278_Rev2p1p1 to use
PTL_SKU_* constants instead of PTL_CORE_* constants. This aligns with
the corrected indexing scheme used in the SoC VR configuration code.
TEST=Verify IccLimit value for different SKUs in FSP debug log
Change-Id: I90a5c6e03633ba2b4a0a132ed9f94d8e5c4ff8bf
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91049
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Set CBFS_SIZE to match the SI_BIOS region size defined in each board's
chromeos.fmd file, up to a maximum of 16MiB. This ensures the largest
possible region is available for CBFS use without requiring manual
CBFS_SIZE overrides. The size is capped at 16MiB as that is the
largest area that can be memory mapped, the FIT pointer must be
located in the top 16MiB.
This change applies to all Intel-based Google mainboards with ChromeOS
FMD layouts that explicitly define SI_BIOS region sizes, and which do
not define a default non-ChromeOS FMAP layout (octopus, reef).
For boards with multiple ChromeOS FMD files, CBFS_SIZE is set
conditionally based on ROM size or silicon variant, using the
same logic as to select the ChromeOS FMD file.
This eliminates the need to override CBFS_SIZE when using larger
payloads (e.g., edk2) or multiple payloads, making the default
configuration more flexible.
TEST=build/boot various google boards with edk2 payload without
overriding CBFS_SIZE.
Change-Id: If7ef6cc96afcdd025958c578ad80fd0db641582a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
On these two mainboards, a Gen1 device is connected on PCIe RP #7.
Measurements have shown that a value of -0.137 dB yields an optimal eye
TX mask test.
BUG=none
TEST=Eye TX mask test for PCIe RP #7 passed using an oscilloscope
Change-Id: I2d95e50473e39c325531c6071773a6a3cbb3a1a0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90945
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the HID used from OVTIDB10 to OVTI13B1 for proper attachment
under Windows. Linux/ChromeOS don't use the HID, and so are unaffected
by the change.
TEST=build/boot Win11 on Teliks, verify MIPI camera driver loads
properly.
Change-Id: Ia81bd8cfaf6bb160f4f18214edccdf425d22cf6f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91108
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the corresponding sensor_name value used by the Windows drivers for
each camera sensor. Update the name used for Redrix based on testing.
This value is not used by ChromeOS/Linux.
TEST=build/boot Win11 on redrix, magolor. Verify IPU/MIPI camera works
properly using available drivers.
Change-Id: Id4fba3667f9497f71787e504bf244d54e433e552
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
