mb/lenovo/{t480,t480s,x280}: Enable TBT support

Select the discrete TBT controller driver, and configure the necessary
GPIOs for the Alpine Ridge TBT controller to be fully functional.
Add ACPI to ensure the TBT controller properly handles S3 sleep and
resume. Update the documentation w/r/t TBT functionality.

TEST=build/boot Lenovo T480, boot Linux, verify all TBT-related PCI
devices populated, lower USB-C port works for USB data and PCIe.

Change-Id: Ie5586fa72ed6819b9d1c37373c21605d39bad7b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88490
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Documentation/mainboard/lenovo/skylake.md

@@ -193,8 +193,6 @@ binaries if only flashing the `bios` region.
 
 ## Known Issues
 
-- Alpine Ridge Thunderbolt 3 controller does not work
-  - Lower (right) USB-C port only works for charging/DP alt mode, not USB/PCIe data
 - Some Fn+F{1-12} keys aren't handled correctly
 - Nvidia dGPU is finicky
   - Needs option ROM
@@ -206,6 +204,7 @@ binaries if only flashing the `bios` region.
 
 ## Verified Working
 
+- Alpine Ridge Thunderbolt 3 controller
 - Integrated graphics init with libgfxinit
 - video output: internal (eDP), miniDP
 - ACPI support

src/mainboard/lenovo/sklkbl_thinkpad/Kconfig

@@ -32,6 +32,7 @@ config BOARD_LENOVO_T470S
 config BOARD_LENOVO_T480
 	bool
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select DRIVERS_INTEL_DTBT
 	select SOC_INTEL_KABYLAKE
 	select MEC1653_HAS_DEBUG_UNLOCK
 	select VARIANT_HAS_DGPU
@@ -39,6 +40,7 @@ config BOARD_LENOVO_T480
 config BOARD_LENOVO_T480S
 	bool
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select DRIVERS_INTEL_DTBT
 	select SOC_INTEL_KABYLAKE
 	select VARIANT_HAS_DGPU
 
@@ -52,6 +54,7 @@ config BOARD_LENOVO_T580
 config BOARD_LENOVO_X280
 	bool
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select DRIVERS_INTEL_DTBT
 	select SOC_INTEL_KABYLAKE
 	select HAVE_SPD_IN_CBFS
 

src/mainboard/lenovo/sklkbl_thinkpad/acpi/mainboard.asl

@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}

src/mainboard/lenovo/sklkbl_thinkpad/acpi/sleep.asl

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Prepare discrete TBT controller before sleep */
+Method(MPTS, 1, Serialized) {
+	If (CondRefOf(\TBTS)) {
+		\TBTS()
+	}
+}

src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl

@@ -11,6 +11,7 @@ DefinitionBlock(
 )
 {
 	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
 	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
 

src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c

@@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C18, NONE),
 	PAD_NC(GPP_C19, NONE),
 	PAD_CFG_GPO(GPP_C20, 0, DEEP),					/* EPRIVACY_ON */
-	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_C21, 1, PLTRST),				/* TBT_FORCE_PWR */
 	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
 	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
 
@@ -191,9 +191,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_G1, NONE),
 	PAD_NC(GPP_G2, NONE),
 	PAD_NC(GPP_G3, NONE),
-	PAD_CFG_GPO(GPP_G4, 0, DEEP),					/* TBT_RTD3_PWR_EN */
-	PAD_CFG_GPO(GPP_G5, 0, DEEP),					/* TBT_FORCE_USB_PWR */
-	PAD_CFG_GPO(GPP_G6, 0, DEEP),					/* -TBT_PERST */
+	PAD_CFG_GPO(GPP_G4, 1, PLTRST),					/* TBT_RTD3_PWR_EN */
+	PAD_CFG_GPO(GPP_G5, 1, PLTRST),					/* TBT_FORCE_USB_PWR */
+	PAD_CFG_GPO(GPP_G6, 1, PLTRST),					/* -TBT_PERST */
 	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),		/* -TBT_PCIE_WAKE */
 };
 

src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c

@@ -82,7 +82,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C18, NONE),
 	PAD_NC(GPP_C19, NONE),
 	PAD_CFG_GPO(GPP_C20, 0, DEEP),					/* EPRIVACY_ON */
-	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_C21, 1, PLTRST),					/* TBT_FORCE_PWR */
 	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
 	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
 
@@ -187,9 +187,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_G1, NONE),
 	PAD_NC(GPP_G2, NONE),
 	PAD_NC(GPP_G3, NONE),
-	PAD_CFG_GPO(GPP_G4, 0, DEEP),					/* TBT_RTD3_PWR_EN */
-	PAD_CFG_GPO(GPP_G5, 0, DEEP),					/* TBT_FORCE_USB_PWR */
-	PAD_CFG_GPO(GPP_G6, 0, DEEP),					/* -TBT_PERST */
+	PAD_CFG_GPO(GPP_G4, 1, PLTRST),					/* TBT_RTD3_PWR_EN */
+	PAD_CFG_GPO(GPP_G5, 1, PLTRST),					/* TBT_FORCE_USB_PWR */
+	PAD_CFG_GPO(GPP_G6, 1, PLTRST),					/* -TBT_PERST */
 	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),		/* -TBT_PCIE_WAKE */
 };
 

src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c

@@ -82,7 +82,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C18, NONE),
 	PAD_NC(GPP_C19, NONE),
 	PAD_NC(GPP_C20, NONE),
-	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_C21, 1, PLTRST),				/* TBT_FORCE_PWR */
 	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
 	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
 
@@ -187,10 +187,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_G1, NONE),
 	PAD_NC(GPP_G2, NONE),
 	PAD_NC(GPP_G3, NONE),
-	PAD_CFG_GPO(GPP_G4, 0, DEEP),                                   /* TBT_RTD3_PWR_EN */
-	PAD_CFG_GPO(GPP_G5, 0, DEEP),                                   /* TBT_FORCE_USB_PWR */
-	PAD_CFG_GPO(GPP_G6, 0, DEEP),                                   /* -TBT_PERST */
-	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),             /* -TBT_PCIE_WAKE */
+	PAD_CFG_GPO(GPP_G4, 1, PLTRST),					/* TBT_RTD3_PWR_EN */
+	PAD_CFG_GPO(GPP_G5, 1, PLTRST),					/* TBT_FORCE_USB_PWR */
+	PAD_CFG_GPO(GPP_G6, 1, PLTRST),					/* -TBT_PERST */
+	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),		/* -TBT_PCIE_WAKE */
 
 };