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mb/google/fatcat/var/moonstone: Configure CDCLK frequency for display

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Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to 1 in the moonstone variant
overridetree. This ensures the display engine operates at the required
frequency (442Mhz) for the panel to meet the hardware configuration.

BUG=b:484559627
TEST=Build and boot google/moonstone, verify display initialization.

Change-Id: I4d3d0082f9f221333150bd5b427b3f20e7a2f154
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91236
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2026-02-15 22:29:44 +05:30
commit ae2e78ce31
1 changed files with 2 additions and 0 deletions
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2
src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
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@ -87,6 +87,8 @@ chip soc/intel/pantherlake
register "cnvi_wifi_core" = "true"
register "cnvi_bt_core" = "true"
register "vga_cd_clk_freq_sel" = "CD_CLK_442MHZ"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,