erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/fatcat: Configure CDCLK frequency for display

Browse source 
Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the fatcat
baseboard devicetree. This ensures the display engine operates at the
required frequency for the panel to meet the hardware configuration.

BUG=b:458353982
TEST=Build and boot fatcat/lapis, verify display initialization.

Change-Id: If8812bc66149b402adb7b9159f3a28d35903b785
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Sowmya V 2026-02-17 16:12:23 +05:30 • committed by Subrata Banik
commit 5eb9e9999d
1 changed files with 1 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
View file

@ -141,6 +141,7 @@ chip soc/intel/pantherlake
register "pch_hda_idisp_codec_enable" = "true"
register "disable_progress_bar" = "true"
register "vga_cd_clk_freq_sel" = "CD_CLK_461MHZ"
device domain 0 on
device ref dtt on end