ae2e78ce31
Configure the Core Display Clock (CDCLK) frequency selection by setting the 'vga_cd_clk_freq_sel' register to 1 in the moonstone variant overridetree. This ensures the display engine operates at the required frequency (442Mhz) for the panel to meet the hardware configuration. BUG=b:484559627 TEST=Build and boot google/moonstone, verify display initialization. Change-Id: I4d3d0082f9f221333150bd5b427b3f20e7a2f154 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91236 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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