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mb/google/brask/var/moxoe: Enable PCIe WiFi 7 support

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Add configuration for the PCIe Root Port connected to the WiFi 7 module.

BUG=b:481186489
TEST=Build successfully for moxoe. Verify WiFi 7 functionality on
 moxie.

Change-Id: I8941b587ac35f6c03654de959cc93350b5604b35
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91103
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Kenneth Chan 2026-02-05 16:19:06 +08:00 • committed by Matt DeVillier
commit 61ae24a854
1 changed files with 31 additions and 1 deletions
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32
src/mainboard/google/brya/variants/moxoe/overridetree.cb
View file

@ -13,6 +13,10 @@ fw_config
option TC_USB4 0
option TC_USB3 1
end
field WIFI_TYPE 10
option WIFI_PCIE 0
option WIFI_CNVI 1
end
field USB_HUB 32
option HUB_ABSENT 0
option HUB_PRESENT 1
@ -176,7 +180,9 @@ chip soc/intel/alderlake
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
device generic 0 on
probe WIFI_TYPE WIFI_CNVI
end
end
end
device ref i2c0 on
@ -205,6 +211,30 @@ chip soc/intel/alderlake
end
end
end
device ref pcie_rp5 on
probe WIFI_TYPE WIFI_PCIE
# Enable wlan PCIe 5 using clk 2
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_03"
register "add_acpi_dma_property" = "true"
device pci 00.0 on
probe WIFI_TYPE WIFI_PCIE
end
end
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
register "srcclk_pin" = "2"
device generic 0 on
probe WIFI_TYPE WIFI_PCIE
end
end
end #PCIE5 WLAN card
device ref pcie_rp7 on
chip drivers/net
register "wake" = "GPE0_DW0_07"