Use an additional Realtek NIC MAC programming sequence recently
added to drivers/net/r8168.c.
BUG=https://ticket.coreboot.org/issues/579
TEST=Specified MAC address now recognized and retained by Linux r8169
driver without further work.
Change-Id: Ia1409874920b2e598e8b8b3c186fc46bd0cef296
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87437
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On mainboard/asus/p8z77-v_le_plus, programmed MAC address is being
reverted with controller resets done at loading and unloading of Linux
r8169 kernel module.
Ghidra examination of vendor BIOS reveals an additional sequence to
program the MAC address into its ERI register block. This patch
adds code to replicate that sequence, gated by a Kconfig so it's
only included where necessary.
BUG=https://ticket.coreboot.org/issues/579
TEST=When applied with mainboard level changes in CB:87437, specified
MAC address now recognized and retained by Linux r8169 driver without
further work.
Change-Id: Iae33e24e564f9fba52acb16138fe89085d9eeb03
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87436
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use a static variable to cache the board ID. It optimizes boot time by
reading the ID once per stage and retaining it for subsequent use.
Rewrite the function to avoid the unnecessary ChromeEC wrapper function.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I166ca1abdf7838f91319d0bcf11354055ed93eef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87247
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Ziliatech SDVB8D8A34XGCL3N3T as id 2, resulting in the list below:
DRAM Part Name ID to assign
MT53E512M32D1NP-046 WT:B 0 (0000)
K4U6E3S4AA-MGCR 0 (0000)
H54G46CYRBX267 0 (0000)
CXDB4CBAM-ML-A 1 (0001)
SDVB8D8A34XGCL3N3T 2 (0010)
BUG=b:398700043
BRANCH=None
TEST=Use part_id_gen to generate related settings
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: If85ea78828ab520d10dcbe4ccbba685ac1746c51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87440
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit introduces a Kconfig option to define the GPIO pin used
for the Google Security Chip (GSC) to Application Processor (AP)
interrupt on the Bluey mainboard.
Previously, the GPIO_GSC_AP_INT was hardcoded to GPIO 34 in
board.h. This change makes it configurable for any future variants
using Qualcomm X1P-42-100 SoC.
BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.
Change-Id: I5759667158082a80124bf3faa3c56aee50c1be34
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit implements `mainboard_is_hda_codec_enabled` for the Google
Francka mainboard variant. This overrides the default weak HDA common
initialization.
Initialization of the High Definition Audio (HDA) controller, managed by
`azalia_audio_init()` (which handles HDA verb table loading), is now
conditional. It proceeds only if the firmware config
`FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA)` is set. This targets the
ALC256M-CG HDA codec.
This change ensures that HDA verb tables are loaded only when the
ALC256M-CG HDA codec is actively configured for the Francka variant.
Crucially, this prevents attempts to incorrectly load HDA verbs for
other audio interfaces, like SoundWire (SNDW), which might be present
in different Francka hardware configurations.
The header `intelblocks/hda.h` added to support this HDA initialization
logic.
BUG=b:ENTER_FRANCKA_BUG_ID_HERE
TEST=Verified HDA verb table loading is skipped on Francka platforms
when configured with non-HDA audio codecs (e.g., SNDW),
and proceeds as expected when ALC256M-CG HDA is configured
Change-Id: Idbc506c1ad180c7e8ecdec51c3491e6f0518204c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit implements `mainboard_is_hda_codec_enabled()` for the
Google Fatcat mainboard variant. This overrides the default weak HDA
common initialization.
Initialization of the High Definition Audio (HDA) controller,
managed by `azalia_audio_init()` (which handles HDA verb table
loading), is now conditional. It proceeds only if the firmware
config `FW_CONFIG(AUDIO, AUDIO_ALC256_HDA)` is set. This value
(3) specifically targets the ALC256 HDA codec.
This change ensures that HDA verb tables are loaded only when the
ALC256 HDA codec is actively configured for the Fatcat variant.
Crucially, this prevents attempts to incorrectly load HDA verbs
for other audio interfaces, like SoundWire (SNDW) or I2S, which might
be present in different Fatcat hardware configurations.
The header file `intelblocks/hda.h` added for this. As a minor stylistic
update, header inclusions in this file are also alphabetized.
BUG=b:413638298
TEST=Verified HDA verb table loading is skipped on Fatcat platforms
when configured with non-HDA audio codecs (e.g., SNDW, I2S),
and proceeds as expected when ALC256 HDA is configured.
Change-Id: Ifc158b7d15c763cc07d28154259b7e64709bea16
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit refactors the HDA initialization within the common Intel
SoC block to provide mainboard-level customization.
A new weak function, mainboard_is_hda_codec_enabled(), is
introduced. The `hda_init()` function invokes `azalia_audio_init()` when
`CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB)` is enabled and
`mainboard_is_hda_codec_enabled()` is also true.
The default (weak) implementation of `mainboard_is_hda_codec_enabled()`
simply returns `true`, ensuring that the original behavior is maintained
for mainboards that do not provide an override.
This change allows specific mainboards to implement their own
`mainboard_is_hda_codec_enabled()` to specify if hardware design has
support for HDA codec depending upon the firmware config (FW_CONFIG) for
the audio subsystem.
BUG=b:413638298
TEST=Able to build and boot google/fatcat.
Change-Id: Ided1413e828f6bc3421e538a969c38e15b5f3116
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit removes the `device ref npk on end` from the
`overridetree.cb` files for the `fatcat` and `francka` variants
of the `google/fatcat` mainboard. This effectively disables
the NPK device for these configurations (because `npk` is default
set to disable).
BUG=b:328770565
TEST=Able to build google/fatcat.
Change-Id: I9dda20552781af6b29a2156cbc1e3bea352c5836
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
GPP_E9 was wrongly configured to NF1 instead of NF2 i.e. ISH_GP4.
Reference: Intel doc#648094
BUG=b:410645679
TEST=Check GPIO config in the OS.
Change-Id: I43e3ec2e29138d59ed82e5ff4b264ab8dc3a39fb
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87471
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yuval Peress <peress@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit imports changes from mb/google/fatcat to mb/intel/ptlrvp as
of coreboot codebase commit 010cfa2842
("doc/internals/devicetree_language: multiple segment groups
supported").
Here is the list of imported commits:
- commit 9495063993 ("mainboard/google/fatcat: Fix SMBIOS Processor
upgrade info")
- commit 27f3427f4a ("mb/google/fatcat/var/fatcat: Update GSPI0 CS pin
for FPS")
- commit c41af2d43c ("mb/google/fatcat/var/fatcat: Update THC
Interrupt for Touchpad Development")
- commit b5dea9fa99 ("mb/google/fatcat/var/francka: Add Write Protect
GPIO to cros_gpios")
- commit ef80ccbc43 ("mb/google/fatcat: Disable EC software sync for
Microchip EC")
- commit 9f39d6ec5e ("mb/google/fatcat: Enable HAVE_SLP_S0_GATE for
felino and francka")
- commit eb85dfae1f ("mb/google/fatcat: Configure GPIO_SLP_S0_GATE for
francka and felino")
- commit 0fc2422e88 ("mb/google/fatcat: Implement S0ix hooks aka
`MS0X` method")
- commit 1fa5ab805b ("mb/google/fatcat: Remove unnecessary CNVi core
variables settings")
- commit 5c0340349e ("mb/google/fatcat: Rationalize Wi-Fi and
Bluetooth combinations")
- commit 275beb93db ("mb/google/fatcat: Conditionally check for barrel
charger")
- commit e9b020f02e ("mb/google/fatcat: Allow board-specific FSP-M UPD
override")
- commit 3a88eb8cb6 ("mb/google/fatcat: Enable HDA SDI based on FW
config")
- commit 0ac2058dbe ("mb/google/fatcat: Increase sagv_freq_mhz for
work point #1 to #3")
- commit 6e529e7c06 ("mb/google/fatcat: Add Intel Touch support for
touchscreen and touchpad")
Overall, these commits aim to improve the configuration, performance,
and compatibility of the Intel Panther Lake Reference Validation
Platform (PTLRVP) mainboard across various aspects, including processor
upgrade support, peripheral integration, power management, and audio
functionality.
TEST=Successful boot with a ptlrvp image on a Fatcat board.
Change-Id: Ie27763a367d8d53c64ad78d26909f1068af3c819
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87223
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On recent AMD platforms the VRT bit in the StatusD register is
read-writeable and set every 1024msec when RTC power is good.
This leads to a timeout in RtcWaitToUpdate() waiting for the bit
to be set and the gEfiRealTimeClockArchProtocolGuid won't be installed.
The protocol is critical to boot.
Adjust the code to not clear the VRT bit, as RtcWaitToUpdate() will
return an error, as it assumes the VRT bit is read-only and hardwired
to one as on Intel ICHs. While the timeout could be increased it
would also increase boot time by up to a second.
On platforms where the VRT bit is read-only the introduced code
does the same as before.
Change-Id: I8bc432114c83fa5f5fb35a144e3a35c38ee8a3de
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87415
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Update the DPTF parameters as provided by thermal team.
1. Tcc_offset: 5 -> 3
2. Modify critical policy and passive policy setting
BUG=b:411866724
BRANCH=firmware-trulo-15217.771.B
TEST=build test firmware and verified by thermal team
Change-Id: Id5fda2e8c4985d41d0871454bb808a9cdfedc3e6
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87425
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
This commit adds configurations for both external and internal EC
versions of the PTL RVP board. The changes involve updates to the
Kconfig files to select appropriate EC configurations based on the
specific PTL RVP variant. By organizing these options, it ensures
that the build system selects the right EC components and
configurations, aligning with the specific needs of the board version
in use.
The new configuration for external EC (`BOARD_INTEL_PTLRVP_CHROMEEC`)
enables Chrome EC related config options and enables TPM, whereas
Intel EC (`BOARD_INTEL_PTLRVP`) disables Chrome EC related config
options and uses MOCK TPM.
BUG=none
TEST=Build the firmware for PTL RVP with both external and internal EC
settings, verifying that the correct components are included based on
the chosen configuration. Ensure that the board operates correctly
with the selected EC setup.
Change-Id: Ic3e40f2a19d7ed4f7a16e6e516a284a9a778b9fd
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add GOOGLE OCELOT MAINBOARDS section for src/mb/google/ocelot and
update the maintainers list to add Nick Vaccaro, Pranava Y N, and
Avi Uday as maintainers.
Change-Id: Ia5fc7fcdd5ea2f3588343834dccd86ee2b17f9a8
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87438
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update the default Kconfig values for the google/bluey mainboard
to specify the correct hardware instances/buses used for various
peripherals as per bluey schematics (dated 04/15).
Changes:
- TPM I2C bus set to 0x10.
- ChromeEC SPI bus set to 0xb.
Removes previous TODO placeholders.
BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.
Change-Id: I48283e9f5b9dc1d2f203dadbdf6d4e27566f0a83
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Update the default Kconfig values for the `soc/qualcomm/x1p42100`
to specify the correct hardware instances/buses used for various
peripherals as per datasheet for bluey (dated 04/15).
Changes:
- Boot SPI flash bus set to 24.
- Console UART instance set to 21.
- Select FIXED_UART_FOR_CONSOLE Kconfig as UART is not really
selectable due to GPIO Function 0 (bit-bang mode) default
configuration.
Additionally, remove previous used TODO placeholders.
BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.
Change-Id: Ia053edb731f7e08c98ffa3fe273ddd1c97b651bb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87272
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds QUP-SE entries as applicable for the Qualcomm X1P-42-100
SoC.
This includes:
- Add new entries for QUPV3_2 SEs.
- Update base addresses for all QUP-SEs.
- Base GPIO pin function assignments.
- Definition and GPIO mapping for relevant QUP Serial Engines (SEs).
- GPIO mapping for the QSPI interface.
Additionally, update GPIO PINS for QSPI and UART.
BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.
Change-Id: Ib0535aa5dfadef8c412c5e9dd51859068539821f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
TEST=build/boot google/panther with CFR options enabled.
Change-Id: I5067e7a69f1f53f0f93d337198d3c349facec086
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
TEST=build/boot google/guado with CFR options enabled.
Change-Id: Iaf9950a3b446b1b55d836e54e8b231d047571768
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87387
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some ITE ECs take long time (15-20s) to complete flash erase operation
during EC software sync. Increasing the timeout value to 30s avoids
EC_CMD_FLASH_ERASE command from timing out. As this is just a timeout
value, it should not have any effect on the boot time.
BUGS=b:386920751, b:412210635
TEST= Verify that the EC_CMD_FLASH_ERASE(0x13) is not timing out while
performing EC sync. Below error is avoided,
```
[ERROR] Timeout waiting for EC process command 19!
[INFO ] VB2:update_ec() vb2ex_ec_update_image(select) returned 0x10000001
[INFO ] VB2:vb2api_fail() Need recovery, reason: 0x26 / 0x1
[INFO ] VB2:sync_ec() update_ec(ctx, select_rw) returned 0x10000001
[INFO ] VB2:vb2api_fail() Need recovery, reason: 0x26 / 0x1
[INFO ] VB2:vb2api_ec_sync() ec_sync_phase2(ctx) returned 0x10000001
[INFO ] Saving nvdata
[ERROR] EC software sync failed (0x10000001), rebooting
[INFO ] board_reset() called!
[INFO ] full_reset() called!
```
Change-Id: Id7bfa620e8c19d5b162b60e5cc37003ff339b589
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87427
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I925002958b5de93e833f06fddf772e5334a7bdb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: Iaddaf56563bd5916bc27d99171af48bf46127052
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87399
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Create the pujjocento variant of the nissa reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=b:409254508
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJOCENTO
Change-Id: I33b0642624ba67f53126e92976096ba53750ae89
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87419
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This commit introduces basic support for the google/bluey mainboard,
based on the Qualcomm X1P-42-100 SoC.
Changes:
- Add placeholder mainboard callbacks to enable control flow from /lib
and Qualcomm SoC code.
- Populate the bluey mainboard directory with a copy of the herobrine
codebase, removing SoC/mainboard-specific implementations.
This provides a minimal working build for google/bluey, allowing
upstream builders to compile the mainboard. This facilitates easier
verification of subsequent changes.
BUG=b:404985109
TEST=Successfully built google/bluey with Qualcomm X1P-42-100 SoC.
Change-Id: Id0da1846b8aef6f4ef4345be9cd803aa60406cdf
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86973
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a basic SoC framework for the Qualcomm
X1P-42-100, enabling initial build integration.
Key changes:
- Add placeholder SoC callbacks to facilitate control flow from /lib
and Qualcomm common code.
- Populate the x1p42100 SoC directory with a copy of the SC7280
codebase, with SoC-specific implementations removed.
This provides a foundational structure for X1P-42-100 development
within the `soc/qualcomm/x1p42100` directory, ensuring the upstream
builder can successfully compile the SoC code.
This allows for incremental development and integration.
Reference Document: X1P42100 Hardware Register Description
BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.
Change-Id: I6358177b9c6dc26967d364a2056a62d8ca77f89b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add a Kconfig to support passing `LOAD_OPTION_ROMS=TRUE` as a build
parameter in order to enable edk2 support for dGPUs.
Change-Id: I05444425d1cb98b023681639389949bf3f3b8e9c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87407
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Some SoC like Glinda,
1. It has multiple L3 caches block, each identified by a unique cache
UID. Each core is associated with a specific L3 cache, which can be
determined based on the CPU core ID.
2. Each CPU core have slightly different CPU boost frequency.
For L3 cache info in DMI table type 7, the default implementation
(x86_get_cpu_cache_info) retrieves cache information only for the
current core and assumes that the same L3 cache is shared across all
cores.
To accurately determine the total L3 cache size:
1. Retrieves L3 cache information for each CPU core.
2. Identifies the unique cache ID associated with each core.
3. Aggregates cache sizes for all unique cache IDs to compute the
total L3 cache size, ensuring correct summation even when L3 cache
blocks have different sizes.
Additionally to get core max boost frequency,
1. Determine max boost frequency among all cores & update
smbios_cpu_get_max_speed_mhz such that it return max of all cores.
TEST=Build for Glinda SoC & check output of `dmidecode -t 7` &
`dmidecode -t 4`. Verify DMI Type7 table to report L3 cache size as 24MB
(16 + 8) & Also verify DMI Type4 'Max Speed: 5408 MHz' which is maximum
boost clock frequency.
Change-Id: I2569a9c744f7f41e4df692626e77a178184b7e0e
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This enables the utility crossystem to access WP GPIO,
`GPIO_PCH_WP` aka GPP_C08 is part of PTL GPIO community 0
therefore add `CROS_GPIO_DEVICE0_NAME` into the `cros_gpios` lists.
BUG=b:409472563
TEST= wpsw_cur in crossystem reads the correct gpio
Change-Id: Ia21b95d220d8df30fb3aa73b4c71047b135a52e6
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87426
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
To promote code reuse and maintainability, move i2c functions to common
folder. The function prototype "mtk_i2c_bus_init(uint8_t bus)" used by
some legacy platforms are changed to "mtk_i2c_bus_init(uint8_t bus,
uint32_t speed)" for better API integration.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I6ac7009f5af4e6379d3f73aec61d0f4abd28471c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87352
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix some ec bits name and indentation.
Change-Id: I23407e4e7be661980c16ef96dd0efabb3898e3da
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87304
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add DT, WLAN, WWLAN, TB and XGBE port descriptors
according to PI source package #67683 (NDA).
Change-Id: Iccc74fd03f6833112b370ba503d9d33033609c5b
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The parameter CPU isn't used, thus drop it.
Change-Id: Ie7f6179f0545f905463752e94243b438143d8234
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Update the default branch used for MrChromebox's edk2 fork from 2024-08
to 2025-02. This updated branch has been rebased on the latest upstream
stable tag (edk2-stable202502), and updates the EFI revocation database
used for SecureBoot. It also adds support for the CFR-based setup menu
and configuration management, and support for running OpROMs on
external dGPUs.
TEST=build/boot google boards link, panther, lulu, reef, ampton, akemi,
banshee, zork, dewatt, frostflow with edk2 payload selected.
Change-Id: I1f900d0e33e88d747547a1f5218445bb0cce4e4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87406
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Ensure all boards configure these two GPIOs to NF1.
Change-Id: Ie8a222bff349a427083adb1c4d7ca73a41de3095
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This patch adds Wildcat Lake-specific CPU and PCIe device IDs to the
header files and driver-specific code.
Reference:
Wildcat Lake Processor Prelim External Device IDs (820363)
BUG=b:394208231
TEST=Verified on Wildcat Lake Simulation Platform
Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87262
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a new static function `disable_vr_settings_on_pantherlake_h()`
to disable Voltage Regulator (VR) settings when a Panther Lake H System
on Chip (SoC) is detected.
The existing VR configurations, introduced by commit d19dd192db
("mb/google/fatcat: Add PTL-U Fast VMode Voltage Regulator settings"),
are optimized for Panther Lake U SoC, which can cause performance issues
on Panther Lake H boards under stress due to the I_TRIP value being
lower than what the device could actually use. By disabling these
settings, the Firmware Support Package (FSP) falls back to default
values for the SoC, which are more suitable.
TEST=Observe the "Disabling VR settings on PTL-H" log during a boot test
on a Panther Lake H variant.
Change-Id: Ifc371212259fa724425158ad9ebadebd30c81705
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update gpio configuration to match ocelot schematic.
BUG=b:412736286
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it compiles without error.
Change-Id: Id2e2eb9fdf008445124e99393fe4b192ccb27f5d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Update the FW_CONFIG to correspond to the Google Ocelot hardware SKUs
and remove code that is no longer needed due to the FW_CONFIG changes.
Removed support for AUDIO_ALC722_SNDW, AUDIO_MAX98360_ALC56821_I2S,
AUDIO_MAX98373_ALC5682_SNDW, TOUCHSCREEN_LPSS_I2C, UFC_MIPI, UFC_USB,
WFC_MIPI and WFC_USB.
Added support for AUDIO_ALC721_SNDW, DISPLAY_TOUCH_PRESENT, and
DISPLAY_NO_TOUCH_PRESENT.
BUG=b:412736286
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it compiles without error.
Change-Id: I5fd7010230a3f17005f5ca395ffaca0724a615e9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I97d5d8b78cc9e5516dbfc64f81a925b1715b941b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: I1c51e653a9e34bb7f5ac07bcae8481be269f83cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
