mb/google/brya: Create pujjocento variant
Create the pujjocento variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0) BUG=b:409254508 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJOCENTO Change-Id: I33b0642624ba67f53126e92976096ba53750ae89 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87419 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
This commit is contained in:
Kun Liu
Subrata Banik
parent
7da36ad79a
commit
fe881c990c
13 changed files with 1356 additions and 0 deletions
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@ -501,6 +501,12 @@ config BOARD_GOOGLE_PUJJONIRU
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select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
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select SOC_INTEL_TWINLAKE
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config BOARD_GOOGLE_PUJJOCENTO
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select BOARD_GOOGLE_BASEBOARD_TRULO
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
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select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
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config BOARD_GOOGLE_QUANDISO
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select BOARD_GOOGLE_BASEBOARD_NISSA
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select CHROMEOS_WIFI_SAR if CHROMEOS
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@ -861,6 +867,7 @@ config DRIVER_TPM_I2C_BUS
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default 0x0 if BOARD_GOOGLE_PUJJOGATWIN
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default 0x0 if BOARD_GOOGLE_MELIKS
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default 0x0 if BOARD_GOOGLE_EPIC
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default 0x0 if BOARD_GOOGLE_PUJJOCENTO
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config DRIVER_TPM_I2C_ADDR
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hex
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@ -946,6 +953,7 @@ config TPM_TIS_ACPI_INTERRUPT
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default 13 if BOARD_GOOGLE_PUJJOGATWIN
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default 13 if BOARD_GOOGLE_MELIKS
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default 13 if BOARD_GOOGLE_EPIC
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default 13 if BOARD_GOOGLE_PUJJOCENTO
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree_pujjogatwin.cb" if BOARD_GOOGLE_PUJJOGATWIN
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@ -1039,6 +1047,7 @@ config MAINBOARD_PART_NUMBER
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default "Pujjogatwin" if BOARD_GOOGLE_PUJJOGATWIN
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default "Meliks" if BOARD_GOOGLE_MELIKS
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default "Epic" if BOARD_GOOGLE_EPIC
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default "Pujjocento" if BOARD_GOOGLE_PUJJOCENTO
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config VARIANT_DIR
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default "agah" if BOARD_GOOGLE_AGAH
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@ -1117,6 +1126,7 @@ config VARIANT_DIR
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default "pujjoga" if BOARD_GOOGLE_PUJJOGATWIN
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default "meliks" if BOARD_GOOGLE_MELIKS
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default "epic" if BOARD_GOOGLE_EPIC
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default "pujjocento" if BOARD_GOOGLE_PUJJOCENTO
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config VBOOT
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select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) || BOARD_GOOGLE_RULL
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@ -229,3 +229,6 @@ config BOARD_GOOGLE_MELIKS
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config BOARD_GOOGLE_EPIC
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bool "-> Epic"
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config BOARD_GOOGLE_PUJJOCENTO
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bool "-> Pujjocento"
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@ -0,0 +1,8 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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romstage-y += memory.c
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ramstage-y += gpio.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
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ramstage-y += variant.c
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491
src/mainboard/google/brya/variants/pujjocento/gpio.c
Normal file
491
src/mainboard/google/brya/variants/pujjocento/gpio.c
Normal file
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@ -0,0 +1,491 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <soc/gpio.h>
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#include <types.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* A0 thru A4, A9 and A10 come configured out of reset, do not touch */
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/* A0 : ESPI_IO0 ==> ESPI_SOC_D0_EC */
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/* A1 : ESPI_IO1 ==> ESPI_SOC_D1_EC */
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/* A2 : ESPI_IO2 ==> ESPI_SOC_D2_EC */
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/* A3 : ESPI_IO3 ==> ESPI_SOC_D3_EC */
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/* A4 : ESPI_CS0# ==> ESPI_SOC_CS_EC_L */
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/* A5 : ESPI_ALERT0# ==> NC */
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PAD_NC(GPP_A5, NONE),
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/* A6 : ESPI_ALERT1# ==> NC */
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PAD_NC(GPP_A6, NONE),
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/* A7 : NC ==> SLP_S0_GATE_R */
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PAD_CFG_GPO(GPP_A7, 1, DEEP),
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/* A8 : GPP_A8 ==> WWAN_RF_DISABLE_ODL */
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PAD_CFG_GPO(GPP_A8, 1, DEEP),
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/* A9 : ESPI_CLK ==> ESPI_SOC_CLK */
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/* A10 : ESPI_RESET# ==> ESPI_SOC_RST_EC_L */
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/* A11 : SOC_PD1_INT */
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PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),
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/* A12 : SOC_PEN_DETECT_ODL */
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PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_BOTH),
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/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
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PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
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/* A14 : USB_OC1# */
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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/* A15 : USB_OC2# */
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PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
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/* A16 : USB_OC3# ==> NC */
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PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
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/* A17 : NC */
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PAD_NC(GPP_A17, NONE),
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/* A18 : NC */
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PAD_NC(GPP_A18, NONE),
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/* A19 : NC */
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PAD_NC(GPP_A19, NONE),
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/* A20 : DDSP_HPD2 ==> SOC_HDMI_HPD */
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PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
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/* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
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PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
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/* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
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PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
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/* A23 : GPP_A23 ==> NC */
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PAD_NC(GPP_A23, NONE),
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/* B0 : CORE_VID0 ==> VCCIN_AUX_VID0 */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* B1 : CORE_VID1 ==> VCCIN_AUX_VID1 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* B2 : NC */
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PAD_NC(GPP_B2, NONE),
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/* B3 : CPU_GP2 ==> GYRO_SENSOR_INT */
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PAD_CFG_GPI_APIC(GPP_B3, NONE, PWROK, LEVEL, INVERT),
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/* B4 : PROC_GP3 ==> ACC_SENSOR_INT */
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PAD_CFG_GPI_APIC(GPP_B4, NONE, PWROK, LEVEL, INVERT),
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/* B5 : GPP_B5 ==> ISH_I2C0_SENSOR_SCL */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
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/* B6 : GPP_B6 ==> ISH_I2C0_SENSOR_SDA */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
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/* B7 : I2C3_SDA ==> SOC_I2C_SAR_SDA */
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PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
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/* B8 : I2C3_SCL ==> SOC_I2C_SAR_SCL */
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PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
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/* B9 : Not available */
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PAD_NC(GPP_B9, NONE),
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/* B10 : Not available */
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PAD_NC(GPP_B10, NONE),
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/* B11 : SOC_PD0_INT# */
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PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
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/* B12 : SLP_S0# ==> PM_SLP_S0# */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* B13 : PLTRST# ==> PLT_RST_L */
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PAD_CFG_NF_LOCK(GPP_B13, NONE, NF1, LOCK_CONFIG),
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/* B14 : ACZ_SPKR */
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
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/* B15 : NC */
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PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
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/* B16 : GPP_B16 ==> I2C_TOUCHPAD_SDA */
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PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
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/* B17 : GPP_B17 ==> I2C_TOUCHPAD_SCL */
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PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
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/* B18 : GPP_B18 ==> GPP_B18_STRAP */
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PAD_NC(GPP_B18, NONE),
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/* B19 : Not available */
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PAD_NC(GPP_B19, NONE),
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/* B20 : Not available */
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PAD_NC(GPP_B20, NONE),
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/* B21 : Not available */
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PAD_NC(GPP_B21, NONE),
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/* B22 : Not available */
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PAD_NC(GPP_B22, NONE),
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/* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
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PAD_NC(GPP_B23, NONE),
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/* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C1 : SMBDATA ==> TCHSCR_RST_L */
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PAD_CFG_GPO(GPP_C1, 1, DEEP),
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/* C2 : SMBALERT# ==> GPP_C2_STRAP */
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PAD_NC(GPP_C2, NONE),
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/* C3 : EN_PP3300_UCAM_X */
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PAD_CFG_GPO_LOCK(GPP_C3, 1, LOCK_CONFIG),
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/* C4 : TCHSCR_REPORT_EN */
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PAD_CFG_GPO(GPP_C4, 0, DEEP),
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/* C5 : SML0ALERT# ==> GPP_C5_STRAP */
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PAD_NC(GPP_C5, NONE),
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/* C6 : SML1_SMBCLK */
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
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/* C7 : SML1_SMBDATA */
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
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/* D0 : NC */
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PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
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/* D1 : ISH_GP1 ==> SOC_GSEN2_INT# */
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PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
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/* D2 : NC */
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PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
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/* D3 : ISH_GP3 ==> WCAM_RST_L */
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PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
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/* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */
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PAD_CFG_GPO(GPP_D4, 1, DEEP),
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/* D5 : NC */
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PAD_NC(GPP_D5, NONE),
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/* D6 : SRCCLKREQ1# ==> WWAN_EN */
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PAD_CFG_GPO(GPP_D6, 1, DEEP),
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/* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
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/* D8 : SRCCLKREQ3# ==> NC */
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PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
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/* D9 : NC */
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PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
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/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
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PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
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/* D11 : NC */
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PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
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/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
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PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
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/* D13 : UART0_ISH_RX_DBG_TX */
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PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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/* D14 : UART0_ISH_TX_DBG_RX */
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PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
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/* D15 : ISH_UART0_RTS# ==> EN_PP2800_WCAM_X */
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PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG),
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/* D16 : ISH_UART0_CTS# ==> EN_PP1800_PP1200_WCAM_X */
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PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG),
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/* D17 : NC */
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PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
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/* D18 : NC */
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PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
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/* D19 : I2S_MCLK1_OUT ==> NC */
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PAD_NC(GPP_D19, NONE),
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/* E0 : SOC_PEN_DETECT_R_ODL */
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PAD_CFG_GPI_INT(GPP_E0, NONE, PLTRST, EDGE_BOTH),
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/* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_0 */
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PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG),
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/* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
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PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
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/* E3 : PROC_GP0 ==> MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_E3, NONE, DEEP),
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/* E4 : NC */
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PAD_NC(GPP_E4, NONE),
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/* E5 : NC */
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PAD_NC(GPP_E5, NONE),
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/* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */
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PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
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/* E7 : NC */
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PAD_NC(GPP_E7, NONE),
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/* E8 : GPP_E8 ==> WLAN_DISABLE_L */
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PAD_CFG_GPO(GPP_E8, 1, DEEP),
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/* E9 : NC */
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PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
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/* E10 : EN_PP3300_WLAN_X */
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PAD_CFG_GPO(GPP_E10, 0, DEEP),
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/* E11 : TCHSCR_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, INVERT),
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/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E12, NONE, LOCK_CONFIG),
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/* E13 : THC0_SPI1_IO0 ==> SINGLE CHANNEL*/
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PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
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/* E14 : DDSP_HPDA ==> EDP_HPD */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* E15 : NC */
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PAD_NC(GPP_E15, NONE),
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/* E16 : NC */
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PAD_NC(GPP_E16, NONE),
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/* E17 : WWAN_RST_L */
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PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG),
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/* E18 : NC */
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PAD_NC(GPP_E18, NONE),
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/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
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PAD_NC(GPP_E19, NONE),
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/* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */
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PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
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/* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */
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PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
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/* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */
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PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
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/* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */
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PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
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/* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
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PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
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/* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */
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PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
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/* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
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PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
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/* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */
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PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
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/* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */
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PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
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/* F5 : CRF_XTAL_CLKREQ ==> CNV_CLKREQ0 */
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PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
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/* F6 : CNV_PA_BLANKING ==> WLAN_WWAN_COEX_3 */
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PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
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/* F7 : GPP_F7 ==> GPP_F7_STRAP */
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PAD_NC(GPP_F7, NONE),
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/* F8 : Not available */
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PAD_NC(GPP_F8, NONE),
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/* F9 : Not available */
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PAD_NC(GPP_F9, NONE),
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/* F10 : GPP_F10 ==> GPP_F10_STRAP */
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PAD_NC(GPP_F10, NONE),
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/* F11 : NC */
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PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
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/* F12 : NC */
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PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
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/* F13 : NC */
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PAD_NC(GPP_F13, NONE),
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/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
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PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PWROK, LEVEL, INVERT),
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/* F15 : NC */
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PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
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/* F16 : NC */
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PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
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/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
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PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG),
|
||||
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
|
||||
PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
|
||||
/* F19 : Not available */
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
/* F20 : Not available */
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
/* F21 : Not available */
|
||||
PAD_NC(GPP_F21, NONE),
|
||||
/* F22 : NC */
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
/* F23 : V1P05_CTRL ==> V1P05EXT_CTRL */
|
||||
PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
|
||||
|
||||
/* H0 : GPP_H0_STRAP */
|
||||
PAD_NC(GPP_H0, NONE),
|
||||
/* H1 : GPP_H1_STRAP */
|
||||
PAD_NC(GPP_H1, NONE),
|
||||
/* H2 : GPP_H2_STRAP */
|
||||
PAD_NC(GPP_H2, NONE),
|
||||
/* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
|
||||
PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG),
|
||||
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
|
||||
PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG),
|
||||
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
|
||||
PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG),
|
||||
/* H6 : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
/* H7 : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
/* H8 : MIPI_WCAM_SDA */
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
|
||||
/* H9 : MIPI_WCAM_SCL */
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
|
||||
/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
/* H12 : GPP_H12 ==> NC */
|
||||
PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
|
||||
/* H13 : GPP_H13 ==> NC */
|
||||
PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
|
||||
/* H14 : Not available */
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
/* H15 : DDPB_CTRLCLK ==> SOC_DP2_CTRL_CLK */
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
/* H16 : Not available */
|
||||
PAD_NC(GPP_H16, NONE),
|
||||
/* H17 : DDPB_CTRLDATA ==> SOC_DP2_CTRL_DATA */
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
/* H18 : PROC_C10_GATE# ==> CPU_C10_GATE# */
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
/* H19 : SAR_INT_L */
|
||||
PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
|
||||
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
|
||||
PAD_CFG_GPO(GPP_H20, 1, DEEP),
|
||||
/* H21 : NC */
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
/* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
|
||||
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
|
||||
/* H23 : GPP_H23 ==> WWAN_SAR_DETECT_ODL */
|
||||
PAD_CFG_GPO(GPP_H23, 1, DEEP),
|
||||
|
||||
/* R0 : HDA_BCLK ==> HDA_BIT_CLK */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
/* R1 : HDA_SYNC ==> HDA_SYNC */
|
||||
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1),
|
||||
/* R2 : HDA_SDO ==> HDA_SDOUT */
|
||||
PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1),
|
||||
/* R3 : HDA_SDI0 ==> HDA_SDIN0 */
|
||||
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1),
|
||||
/* R4 : HDA_RST# ==> HDA_RST# */
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
/* R5 : HDA_SDI1 ==> HDA_SDIN1 */
|
||||
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1),
|
||||
/* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */
|
||||
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
|
||||
/* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */
|
||||
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
|
||||
|
||||
/* S0 : I2S_SPK_BCLK_R ==> NC */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
/* S1 : I2S_SPK_LRCK_R ==> NC */
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
/* S2 : DMIC_CKL_A0 ==> NC */
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
/* S3 : DMIC_DATA0 ==> NC */
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
/* S4 : NC */
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
/* S5 : NC */
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
/* S6 : NC */
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
/* S7 : NC */
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
|
||||
/* I5 : NC */
|
||||
PAD_NC(GPP_I5, NONE),
|
||||
/* I7 : EMMC_CMD ==> NC */
|
||||
PAD_NC(GPP_I7, NONE),
|
||||
/* I8 : EMMC_DATA0 ==> NC */
|
||||
PAD_NC(GPP_I8, NONE),
|
||||
/* I9 : EMMC_DATA1 ==> NC */
|
||||
PAD_NC(GPP_I9, NONE),
|
||||
/* I10 : EMMC_DATA2 ==> NC */
|
||||
PAD_NC(GPP_I10, NONE),
|
||||
/* I11 : EMMC_DATA3 ==> NC */
|
||||
PAD_NC(GPP_I11, NONE),
|
||||
/* I12 : EMMC_DATA4 ==> NC */
|
||||
PAD_NC(GPP_I12, NONE),
|
||||
/* I13 : EMMC_DATA5 ==> NC */
|
||||
PAD_NC(GPP_I13, NONE),
|
||||
/* I14 : EMMC_DATA6 ==> NC */
|
||||
PAD_NC(GPP_I14, NONE),
|
||||
/* I15 : EMMC_DATA7 ==> NC */
|
||||
PAD_NC(GPP_I15, NONE),
|
||||
/* I16 : EMMC_RCLK ==> NC */
|
||||
PAD_NC(GPP_I16, NONE),
|
||||
/* I17 : EMMC_CLK ==> NC */
|
||||
PAD_NC(GPP_I17, NONE),
|
||||
/* I18 : EMMC_RESET# ==> NC */
|
||||
PAD_NC(GPP_I18, NONE),
|
||||
|
||||
/* GPD0 : BATLOW# ==> SOC_BATLOW_L */
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* GPD1 : ACPRESENT ==> SOC_ACPRESENT */
|
||||
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* GPD2 : EC_SOC_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPD2, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* GPD3 : PWRBTN# ==> EC_SOC_PWR_BTN_ODL */
|
||||
PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
|
||||
/* GPD4 : SLP_S3# ==> SLP_S3_L */
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* GPD5 : SLP_S4# ==> SLP_S4_L */
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* GPD6 : SLP_A# ==> NC */
|
||||
PAD_NC(GPD6, NONE),
|
||||
/* GPD7 : GPD7_STRAP */
|
||||
PAD_NC(GPD7, NONE),
|
||||
/* GPD8 : SUSCLK ==> PCH_SUSCLK */
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* GPD9 : NC */
|
||||
PAD_NC(GPD9, NONE),
|
||||
/* GPD10 : SLP_S5# ==> NC */
|
||||
PAD_NC(GPD10, NONE),
|
||||
/* GPD11 : NC */
|
||||
PAD_NC(GPD11, NONE),
|
||||
|
||||
/* Configure the unused virtual CNVi Bluetooth UART pads to NC mode. */
|
||||
/* vCNV_BT_UART_TXD */
|
||||
PAD_NC(GPP_VGPIO_6, NONE),
|
||||
/* vCNV_BT_UART_RXD */
|
||||
PAD_NC(GPP_VGPIO_7, NONE),
|
||||
/* vCNV_BT_UART_CTS_B */
|
||||
PAD_NC(GPP_VGPIO_8, NONE),
|
||||
/* vCNV_BT_UART_RTS_B */
|
||||
PAD_NC(GPP_VGPIO_9, NONE),
|
||||
|
||||
/* Configure the unused vUART for Bluetooth pads to NC mode. */
|
||||
/* vUART0_TXD */
|
||||
PAD_NC(GPP_VGPIO_18, NONE),
|
||||
/* vUART0_RXD */
|
||||
PAD_NC(GPP_VGPIO_19, NONE),
|
||||
/* vUART0_CTS_B */
|
||||
PAD_NC(GPP_VGPIO_20, NONE),
|
||||
/* vUART0_RTS_B */
|
||||
PAD_NC(GPP_VGPIO_21, NONE),
|
||||
|
||||
/* Configure the virtual CNVi Bluetooth I2S GPIO Pads.*/
|
||||
/* BT_I2S_BCLK */
|
||||
PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
|
||||
/* BT_I2S_SYNC */
|
||||
PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
|
||||
/* BT_I2S_SDO */
|
||||
PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
|
||||
/* BT_I2S_SDI */
|
||||
PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
|
||||
/* SSP2_SCLK */
|
||||
PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
|
||||
/* SSP2_SFRM */
|
||||
PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
|
||||
/* SSP_TXD */
|
||||
PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
|
||||
/* SSP_RXD */
|
||||
PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */
|
||||
PAD_CFG_GPO(GPP_C0, 1, DEEP),
|
||||
/* C1 : SMBDATA ==> TCHSCR_RST_L */
|
||||
PAD_CFG_GPO(GPP_C1, 1, DEEP),
|
||||
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* E3 : PROC_GP0 ==> SOC_WP_OD */
|
||||
PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
|
||||
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
/* E13 : THC0_SPI1_IO0 ==> SINGLE CHANNEL */
|
||||
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
|
||||
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
|
||||
PAD_CFG_GPO(GPP_H20, 0, DEEP),
|
||||
};
|
||||
|
||||
/* Fill romstage gpio configuration */
|
||||
static const struct pad_config romstage_gpio_table[] = {
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_gpio_override_table(size_t *num)
|
||||
{
|
||||
*num = 0;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
|
||||
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
DECLARE_CROS_GPIOS(cros_gpios);
|
||||
|
||||
const struct pad_config *variant_romstage_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(romstage_gpio_table);
|
||||
return romstage_gpio_table;
|
||||
}
|
||||
128
src/mainboard/google/brya/variants/pujjocento/hda_verb.c
Normal file
128
src/mainboard/google/brya/variants/pujjocento/hda_verb.c
Normal file
|
|
@ -0,0 +1,128 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256
|
||||
0x10ec12ac, // Subsystem ID
|
||||
0x00000013, // Number of jacks (NID entries)
|
||||
|
||||
AZALIA_RESET(0x1),
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb table */
|
||||
AZALIA_SUBVENDOR(0, 0x10ec12ac),
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
|
||||
/*
|
||||
* DMIC
|
||||
* Requirement is to use PCH DMIC. Hence,
|
||||
* commented out codec's Internal DMIC.
|
||||
* AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
|
||||
* AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
*/
|
||||
|
||||
/* Pin widget 0x14 - Front (Port-D) */
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
/* Pin widget 0x18 - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
|
||||
/* Pin widget 0x19 - MIC2 (Port-F) */
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
|
||||
/* Pin widget 0x1A - LINE1 (Port-C) */
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
|
||||
/* Pin widget 0x1B - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
|
||||
/* Pin widget 0x1D - BEEP-IN */
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
|
||||
/* Pin widget 0x1E - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
|
||||
/* Pin widget 0x21 - HP1-OUT (Port-I) */
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
|
||||
/*
|
||||
* Widget node 0x20 - 1
|
||||
* Codec hidden reset and speaker power 2W/4ohm
|
||||
*/
|
||||
0x0205001A,
|
||||
0x0204C003,
|
||||
0x02050038,
|
||||
0x02047901,
|
||||
/*
|
||||
* Widget node 0x20 - 2
|
||||
* Class D power on Reset
|
||||
*/
|
||||
0x0205003C,
|
||||
0x02040354,
|
||||
0x0205003C,
|
||||
0x02040314,
|
||||
/*
|
||||
* Widget node 0x20 - 3
|
||||
* Disable AGC and set AGC limit to -1.5dB
|
||||
*/
|
||||
0x02050016,
|
||||
0x02040C50,
|
||||
0x02050012,
|
||||
0x0204EBC1,
|
||||
/*
|
||||
* Widget node 0x20 - 4
|
||||
* Set AGC Post gain +1.5dB then Enable AGC
|
||||
*/
|
||||
0x02050013,
|
||||
0x02044023,
|
||||
0x02050016,
|
||||
0x02040E50,
|
||||
/*
|
||||
* Widget node 0x20 - 5
|
||||
* Silence detector enabling + Set EAPD to verb control
|
||||
*/
|
||||
0x02050037,
|
||||
0x0204FE15,
|
||||
0x02050010,
|
||||
0x02040020,
|
||||
/*
|
||||
* Widget node 0x20 - 6
|
||||
* Silence data mode Threshold (-90dB)
|
||||
*/
|
||||
0x02050030,
|
||||
0x0204A000,
|
||||
0x0205001B,
|
||||
0x02040A4B,
|
||||
/*
|
||||
* Widget node 0x20 - 7
|
||||
* Default setting - 1
|
||||
*/
|
||||
0x05750003,
|
||||
0x05740DA3,
|
||||
0x02050046,
|
||||
0x02040004,
|
||||
/*
|
||||
* Widget node 0x20 - 8
|
||||
* support 1 pin detect two port
|
||||
*/
|
||||
0x02050009,
|
||||
0x0204E003,
|
||||
0x0205000A,
|
||||
0x02047770,
|
||||
/*
|
||||
* Widget node 0x20 - 9
|
||||
* To set LDO1/LDO2 as default (used for headset)
|
||||
*/
|
||||
0x02050008,
|
||||
0x02046A0C,
|
||||
0x02050008,
|
||||
0x02046A0C,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
/* Dos beep path - 1 */
|
||||
0x01470C00,
|
||||
0x02050036,
|
||||
0x02047151,
|
||||
0x01470740,
|
||||
/* Dos beep path - 2 */
|
||||
0x0143b000,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __VARIANT_EC_H__
|
||||
#define __VARIANT_EC_H__
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#define WWAN_RST GPP_E17
|
||||
#define T2_OFF_MS 20
|
||||
#define SLP_S0_HDMI_EN GPP_A7
|
||||
#endif
|
||||
111
src/mainboard/google/brya/variants/pujjocento/memory.c
Normal file
111
src/mainboard/google/brya/variants/pujjocento/memory.c
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct mb_cfg variant_memcfg = {
|
||||
.type = MEM_TYPE_LP5X,
|
||||
|
||||
.rcomp = {
|
||||
/* Baseboard uses only 100ohm Rcomp resistors */
|
||||
.resistor = 100,
|
||||
},
|
||||
|
||||
/* DQ byte map */
|
||||
.lpx_dq_map = {
|
||||
.ddr0 = {
|
||||
.dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
|
||||
.dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
|
||||
},
|
||||
.ddr1 = {
|
||||
.dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
|
||||
.dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
|
||||
},
|
||||
.ddr2 = {
|
||||
.dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
|
||||
.dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
|
||||
},
|
||||
.ddr3 = {
|
||||
.dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
|
||||
.dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
|
||||
},
|
||||
.ddr4 = {
|
||||
.dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
|
||||
.dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
|
||||
},
|
||||
.ddr5 = {
|
||||
.dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
|
||||
.dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
|
||||
},
|
||||
.ddr6 = {
|
||||
.dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
|
||||
.dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
|
||||
},
|
||||
.ddr7 = {
|
||||
.dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
|
||||
.dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
|
||||
},
|
||||
},
|
||||
|
||||
/* DQS CPU<>DRAM map */
|
||||
.lpx_dqs_map = {
|
||||
.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
},
|
||||
|
||||
.lp5x_config = {
|
||||
.ccc_config = 0xff,
|
||||
},
|
||||
|
||||
.ect = 1, /* Early Command Training */
|
||||
|
||||
.UserBd = BOARD_TYPE_MOBILE,
|
||||
};
|
||||
|
||||
const struct mb_cfg *variant_memory_params(void)
|
||||
{
|
||||
return &variant_memcfg;
|
||||
}
|
||||
|
||||
int variant_memory_sku(void)
|
||||
{
|
||||
/*
|
||||
* Memory configuration board straps
|
||||
* GPIO_MEM_CONFIG_0 GPP_E1
|
||||
* GPIO_MEM_CONFIG_1 GPP_E2
|
||||
* GPIO_MEM_CONFIG_2 GPP_E3
|
||||
*/
|
||||
gpio_t spd_gpios[] = {
|
||||
GPP_E1,
|
||||
GPP_E2,
|
||||
GPP_E3,
|
||||
};
|
||||
|
||||
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
|
||||
}
|
||||
|
||||
bool variant_is_half_populated(void)
|
||||
{
|
||||
/*
|
||||
* Ideally half_populated is used in platforms with multiple channels to
|
||||
* enable only one half of the channel. Alder Lake N has single channel,
|
||||
* and it would require for new structures to be defined in meminit block
|
||||
* driver for LPx memory configurations. In order to avoid adding new
|
||||
* structures, set half_populated to true. This has the same effect as
|
||||
* having single channel with 64-bit width.
|
||||
*/
|
||||
return true;
|
||||
}
|
||||
|
||||
void variant_get_spd_info(struct mem_spd *spd_info)
|
||||
{
|
||||
spd_info->topo = MEM_TOPO_MEMORY_DOWN;
|
||||
spd_info->cbfs_index = variant_memory_sku();
|
||||
}
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjocento/memory src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt
|
||||
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM-MGCT
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = H58G56CK8BX146
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = K3KL8L80CM-MGCT
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjocento/memory src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt
|
||||
|
||||
DRAM Part Name ID to assign
|
||||
K3KL6L60GM-MGCT 0 (0000)
|
||||
H9JCNNNBK3MLYR-N6E 1 (0001)
|
||||
H58G56CK8BX146 2 (0010)
|
||||
K3KL8L80CM-MGCT 3 (0011)
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# This is a CSV file containing a list of memory parts used by this variant.
|
||||
# One part per line with an optional fixed ID in column 2.
|
||||
# Only include a fixed ID if it is required for legacy reasons!
|
||||
# Generated IDs are dependent on the order of parts in this file,
|
||||
# so new parts must always be added at the end of the file!
|
||||
#
|
||||
# Generate an updated Makefile.mk and dram_id.generated.txt by running the
|
||||
# part_id_gen tool from util/spd_tools.
|
||||
# See util/spd_tools/README.md for more details and instructions.
|
||||
|
||||
# Part Name
|
||||
K3KL6L60GM-MGCT
|
||||
H9JCNNNBK3MLYR-N6E
|
||||
H58G56CK8BX146
|
||||
K3KL8L80CM-MGCT
|
||||
513
src/mainboard/google/brya/variants/pujjocento/overridetree.cb
Normal file
513
src/mainboard/google/brya/variants/pujjocento/overridetree.cb
Normal file
|
|
@ -0,0 +1,513 @@
|
|||
fw_config
|
||||
field WIFI 3 4
|
||||
option WIFI_CNVI_WIFI6E 0
|
||||
option WIFI_PCIE_WIFI7 1
|
||||
option WIFI_UNKNOWN 2
|
||||
end
|
||||
field THERMAL_SOLUTION 9 9
|
||||
option THERMAL_SOLUTION_6W 0
|
||||
option THERMAL_SOLUTION_15W 1
|
||||
end
|
||||
field PDC_CONTROL 11 12
|
||||
option PDC_CONTROL_UNKNOWN 0
|
||||
option PDC_RTS_BYPASS 1
|
||||
option PDC_TI_BYPASS 2
|
||||
end
|
||||
end
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "sagv" = "SaGv_Enabled"
|
||||
|
||||
# GPE configuration
|
||||
register "pmc_gpe0_dw0" = "GPP_A"
|
||||
register "pmc_gpe0_dw1" = "GPP_H"
|
||||
register "pmc_gpe0_dw2" = "GPP_F"
|
||||
|
||||
# S0ix enable
|
||||
register "s0ix_enable" = "true"
|
||||
|
||||
# DPTF enable
|
||||
register "dptf_enable" = "true"
|
||||
|
||||
register "tcc_offset" = "10" # TCC of 90
|
||||
|
||||
# Enable CNVi BT
|
||||
register "cnvi_bt_core" = "true"
|
||||
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch)
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch)
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch)
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A DB (6.2 inch)
|
||||
register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # LTE (3.3 inch)
|
||||
register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch)
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch)
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB))
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB)
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE)
|
||||
|
||||
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
|
||||
|
||||
|
||||
# HD Audio
|
||||
register "pch_hda_dsp_enable" = "1"
|
||||
register "pch_hda_audio_link_hda_enable" = "1"
|
||||
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
|
||||
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
|
||||
register "pch_hda_idisp_codec_enable" = "1"
|
||||
|
||||
# FIVR configurations for rull are disabled since the board doesn't have V1p05 and Vnn
|
||||
# bypass rails implemented.
|
||||
register "ext_fivr_settings" = "{
|
||||
.configure_ext_fivr = 0,
|
||||
}"
|
||||
|
||||
# Enable CNVi BT Audio offload
|
||||
register "cnvi_bt_audio_offload" = "1"
|
||||
|
||||
register "serial_io_i2c_mode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
register "serial_io_gspi_mode" = "{
|
||||
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
register "serial_io_uart_mode" = "{
|
||||
[PchSerialIoIndexUART0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
# FIXME: To be enabled in future based on PNP impact data.
|
||||
# Disable Package C-state demotion for nissa baseboard.
|
||||
register "disable_package_c_state_demotion" = "true"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| I2C0 | TPM. Early init is |
|
||||
#| | required to set up a BAR |
|
||||
#| | for TPM communication |
|
||||
#| I2C1 | Trackpad |
|
||||
#+-------------------+---------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.i2c[0] = {
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST_PLUS,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST_PLUS,
|
||||
.scl_lcnt = 55,
|
||||
.scl_hcnt = 30,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
.i2c[1] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.scl_lcnt = 158,
|
||||
.scl_hcnt = 79,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
.i2c[5] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.scl_lcnt = 150,
|
||||
.scl_hcnt = 85,
|
||||
.sda_hold = 35,
|
||||
}
|
||||
},
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device ref igpu on end
|
||||
device ref dtt on
|
||||
chip drivers/intel/dptf
|
||||
## sensor information
|
||||
register "options.tsr[0].desc" = ""DDR""
|
||||
register "options.tsr[1].desc" = ""charger""
|
||||
register "options.tsr[2].desc" = ""ambient""
|
||||
|
||||
## Active Policy
|
||||
register "policies.active" = "{
|
||||
[0] = {
|
||||
.target = DPTF_CPU,
|
||||
.thresholds = {
|
||||
TEMP_PCT(70, 100),
|
||||
TEMP_PCT(60, 65),
|
||||
TEMP_PCT(42, 60),
|
||||
TEMP_PCT(39, 55),
|
||||
TEMP_PCT(38, 50),
|
||||
TEMP_PCT(35, 43),
|
||||
TEMP_PCT(31, 30),
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.target = DPTF_TEMP_SENSOR_0,
|
||||
.thresholds = {
|
||||
TEMP_PCT(60, 100),
|
||||
TEMP_PCT(55, 65),
|
||||
TEMP_PCT(52, 60),
|
||||
TEMP_PCT(50, 55),
|
||||
TEMP_PCT(48, 50),
|
||||
TEMP_PCT(45, 43),
|
||||
TEMP_PCT(41, 30),
|
||||
}
|
||||
}
|
||||
}"
|
||||
|
||||
## Passive Policy
|
||||
register "policies.passive" = "{
|
||||
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
|
||||
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
|
||||
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 70, 5000),
|
||||
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
|
||||
}"
|
||||
|
||||
## Critical Policy
|
||||
register "policies.critical" = "{
|
||||
[0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
|
||||
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
|
||||
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
|
||||
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
|
||||
}"
|
||||
|
||||
register "controls.power_limits" = "{
|
||||
.pl1 = {
|
||||
.min_power = 5000,
|
||||
.max_power = 6000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 28 * MSECS_PER_SEC,
|
||||
.granularity = 500
|
||||
},
|
||||
.pl2 = {
|
||||
.min_power = 25000,
|
||||
.max_power = 25000,
|
||||
.time_window_min = 32 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 500
|
||||
}
|
||||
}"
|
||||
|
||||
## Charger Performance Control (Control, mA)
|
||||
register "controls.charger_perf" = "{
|
||||
[0] = { 255, 1700 },
|
||||
[1] = { 24, 1500 },
|
||||
[2] = { 16, 1000 },
|
||||
[3] = { 8, 500 }
|
||||
}"
|
||||
|
||||
## Fan Performance Control (Percent, Speed, Noise, Power)
|
||||
register "controls.fan_perf" = "{
|
||||
[0] = { 100, 6000, 220, 2200, },
|
||||
[1] = { 92, 5500, 180, 1800, },
|
||||
[2] = { 85, 5000, 145, 1450, },
|
||||
[3] = { 70, 4400, 115, 1150, },
|
||||
[4] = { 56, 3900, 90, 900, },
|
||||
[5] = { 45, 3300, 55, 550, },
|
||||
[6] = { 38, 3000, 30, 300, },
|
||||
[7] = { 33, 2900, 15, 150, },
|
||||
[8] = { 10, 800, 10, 100, },
|
||||
[9] = { 0, 0, 0, 50, }
|
||||
}"
|
||||
|
||||
## Fan options
|
||||
register "options.fan.fine_grained_control" = "true"
|
||||
register "options.fan.step_size" = "2"
|
||||
|
||||
device generic 0 on
|
||||
probe THERMAL_SOLUTION THERMAL_SOLUTION_6W
|
||||
end
|
||||
end
|
||||
chip drivers/intel/dptf
|
||||
## sensor information
|
||||
register "options.tsr[0].desc" = ""DDR""
|
||||
register "options.tsr[1].desc" = ""charger""
|
||||
register "options.tsr[2].desc" = ""ambient""
|
||||
|
||||
## Active Policy
|
||||
register "policies.active" = "{
|
||||
[0] = {
|
||||
.target = DPTF_CPU,
|
||||
.thresholds = {
|
||||
TEMP_PCT(70, 100),
|
||||
TEMP_PCT(60, 65),
|
||||
TEMP_PCT(42, 58),
|
||||
TEMP_PCT(39, 53),
|
||||
TEMP_PCT(38, 47),
|
||||
TEMP_PCT(35, 43),
|
||||
TEMP_PCT(31, 30),
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.target = DPTF_TEMP_SENSOR_0,
|
||||
.thresholds = {
|
||||
TEMP_PCT(60, 100),
|
||||
TEMP_PCT(55, 65),
|
||||
TEMP_PCT(52, 58),
|
||||
TEMP_PCT(50, 53),
|
||||
TEMP_PCT(48, 47),
|
||||
TEMP_PCT(45, 43),
|
||||
TEMP_PCT(41, 30),
|
||||
}
|
||||
}
|
||||
}"
|
||||
|
||||
## Passive Policy
|
||||
register "policies.passive" = "{
|
||||
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
|
||||
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
|
||||
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 70, 5000),
|
||||
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
|
||||
}"
|
||||
|
||||
## Critical Policy
|
||||
register "policies.critical" = "{
|
||||
[0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
|
||||
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
|
||||
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
|
||||
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
|
||||
}"
|
||||
|
||||
register "controls.power_limits" = "{
|
||||
.pl1 = {
|
||||
.min_power = 14000,
|
||||
.max_power = 15000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 28 * MSECS_PER_SEC,
|
||||
.granularity = 500
|
||||
},
|
||||
.pl2 = {
|
||||
.min_power = 35000,
|
||||
.max_power = 35000,
|
||||
.time_window_min = 32 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 500
|
||||
}
|
||||
}"
|
||||
|
||||
## Charger Performance Control (Control, mA)
|
||||
register "controls.charger_perf" = "{
|
||||
[0] = { 255, 1700 },
|
||||
[1] = { 24, 1500 },
|
||||
[2] = { 16, 1000 },
|
||||
[3] = { 8, 500 }
|
||||
}"
|
||||
|
||||
## Fan Performance Control (Percent, Speed, Noise, Power)
|
||||
register "controls.fan_perf" = "{
|
||||
[0] = { 100, 6000, 220, 2200, },
|
||||
[1] = { 92, 5500, 180, 1800, },
|
||||
[2] = { 85, 5000, 145, 1450, },
|
||||
[3] = { 70, 4400, 115, 1150, },
|
||||
[4] = { 56, 3900, 90, 900, },
|
||||
[5] = { 45, 3300, 55, 550, },
|
||||
[6] = { 38, 3000, 30, 300, },
|
||||
[7] = { 33, 2900, 15, 150, },
|
||||
[8] = { 10, 800, 10, 100, },
|
||||
[9] = { 0, 0, 0, 50, }
|
||||
}"
|
||||
|
||||
## Fan options
|
||||
register "options.fan.fine_grained_control" = "true"
|
||||
register "options.fan.step_size" = "2"
|
||||
|
||||
device generic 1 on
|
||||
probe THERMAL_SOLUTION THERMAL_SOLUTION_15W
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C1 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref tcss_usb3_port2 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C1 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref usb2_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A0 (MLB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A1 (DB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb2_port4 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 LTE""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Camera""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""PCIe Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port8 on
|
||||
probe WIFI WIFI_PCIE_WIFI7
|
||||
probe WIFI WIFI_UNKNOWN
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""CNVi Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port10 on
|
||||
probe WIFI WIFI_CNVI_WIFI6E
|
||||
probe WIFI WIFI_UNKNOWN
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A0 (MLB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A1 (DB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb3_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 WLAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb3_port4 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref shared_sram on end
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
register "enable_cnvi_ddr_rfim" = "true"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device generic 0 on end
|
||||
end
|
||||
probe WIFI WIFI_CNVI_WIFI6E
|
||||
probe WIFI WIFI_UNKNOWN
|
||||
end
|
||||
device ref pcie_rp4 on
|
||||
# PCIe 4 WLAN
|
||||
register "pch_pcie_rp[PCH_RP(4)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_DW1_03"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
# # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E10)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
|
||||
register "srcclk_pin" = "2"
|
||||
device generic 0 on end
|
||||
end
|
||||
probe WIFI WIFI_PCIE_WIFI7
|
||||
probe WIFI WIFI_UNKNOWN
|
||||
end
|
||||
|
||||
device ref i2c0 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end #I2C0
|
||||
device ref i2c5 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||
register "wake" = "GPE0_DW2_14"
|
||||
register "detect" = "1"
|
||||
device i2c 0x15 on end
|
||||
end
|
||||
end
|
||||
device ref heci1 on end
|
||||
device ref ish on
|
||||
chip drivers/intel/ish
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref ufs on end
|
||||
device ref uart0 on end
|
||||
device ref pch_espi on
|
||||
chip ec/google/chromeec
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device ref pmc hidden end
|
||||
device ref hda on
|
||||
chip drivers/sof
|
||||
register "spkr_tplg" = "max98360a"
|
||||
register "jack_tplg" = "rt5682"
|
||||
register "mic_tplg" = "_2ch_pdm0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
38
src/mainboard/google/brya/variants/pujjocento/variant.c
Normal file
38
src/mainboard/google/brya/variants/pujjocento/variant.c
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <chip.h>
|
||||
#include <fw_config.h>
|
||||
#include <sar.h>
|
||||
#include <soc/gpio_soc_defs.h>
|
||||
#include <intelblocks/graphics.h>
|
||||
#include <acpi/acpi.h>
|
||||
#include <acpi/acpigen.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
const char *get_wifi_sar_cbfs_filename(void)
|
||||
{
|
||||
return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
|
||||
}
|
||||
|
||||
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
|
||||
{
|
||||
if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E))
|
||||
|| fw_config_probe(FW_CONFIG(WIFI, WIFI_UNKNOWN))) {
|
||||
printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n");
|
||||
config->cnvi_bt_core = true;
|
||||
config->cnvi_bt_audio_offload = true;
|
||||
} else {
|
||||
printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n");
|
||||
config->cnvi_bt_core = false;
|
||||
config->cnvi_bt_audio_offload = false;
|
||||
}
|
||||
}
|
||||
|
||||
void variant_generate_s0ix_hook(enum s0ix_entry entry)
|
||||
{
|
||||
if (entry == S0IX_ENTRY)
|
||||
acpigen_soc_clear_tx_gpio(SLP_S0_HDMI_EN);
|
||||
else if (entry == S0IX_EXIT)
|
||||
acpigen_soc_set_tx_gpio(SLP_S0_HDMI_EN);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue