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mb/amd/crater: Add missing dxio descriptors

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Add DT, WLAN, WWLAN, TB and XGBE port descriptors
according to PI source package #67683 (NDA).

Change-Id: Iccc74fd03f6833112b370ba503d9d33033609c5b
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Ana Carolina Cabral 2025-04-15 10:19:00 -03:00 • committed by Matt DeVillier
commit 4e55225f2c
2 changed files with 108 additions and 1 deletions
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17
src/mainboard/amd/crater/Kconfig
View file

@ -98,6 +98,23 @@ config ENABLE_EVAL_19V
help
Enable the 19V rail for Eval Card PCIe slot
choice
prompt "XGBE/WWAN/WLAN/DT Selection"
default XGBE_WWAN_WLAN
help
Select the configuration for GPP[0:3] lanes
config XGBE_WWAN_WLAN
bool "XGBE_WWAN_WLAN"
help
Use GPP[0:1] for XGBE (ETH_AIC_SLOT), GPP[2] for WWAN slot and GPP[3] for WLAN slot.
config ETH_AIC_SLOT_ONLY
bool "DT Enablement"
help
Use GPP[0:3] for as PCIE (ETH_AIC_SLOT) only
endchoice
if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig
config EFS_SPI_READ_MODE
default 3 # Quad IO (1-1-4)

92
src/mainboard/amd/crater/port_descriptors_renoir.c
View file

@ -52,6 +52,86 @@
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}, \
}
#define dt_dxio_descriptor { \
.engine_type = PCIE_ENGINE, \
.port_present = true, \
.start_logical_lane = 0, \
.end_logical_lane = 3, \
.device_number = 1, \
.function_number = 2, \
.link_aspm = ASPM_L1, \
.link_aspm_L1_1 = true, \
.link_aspm_L1_2 = true, \
.turn_off_unused_lanes = false, \
.clk_req = CLK_REQ5, \
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}, \
}
#define wwan_dxio_descriptor { \
.engine_type = PCIE_ENGINE, \
.port_present = true, \
.start_logical_lane = 2, \
.end_logical_lane = 2, \
.device_number = 1, \
.function_number = 3, \
.link_aspm = ASPM_L1, \
.link_aspm_L1_1 = true, \
.link_aspm_L1_2 = true, \
.turn_off_unused_lanes = false, \
.clk_req = CLK_REQ2, \
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}, \
}
#define wlan_dxio_descriptor { \
.engine_type = PCIE_ENGINE, \
.port_present = true, \
.start_logical_lane = 3, \
.end_logical_lane = 3, \
.device_number = 2, \
.function_number = 2, \
.link_aspm = ASPM_L1, \
.link_aspm_L1_1 = true, \
.link_aspm_L1_2 = true, \
.turn_off_unused_lanes = false, \
.clk_req = CLK_REQ6, \
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}, \
}
#define tb_dxio_descriptor { \
.engine_type = PCIE_ENGINE, \
.port_present = true, \
.start_logical_lane = 4, \
.end_logical_lane = 7, \
.device_number = 2, \
.function_number = 3, \
.link_aspm = ASPM_L1, \
.link_aspm_L1_1 = true, \
.link_aspm_L1_2 = true, \
.turn_off_unused_lanes = false, \
.clk_req = CLK_REQ4_GFX, \
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}, \
}
/* XGBE ETHERNET PORTS Entry Port 0 */
// XGBE SGMII interface: Physical lane 4, Logical lane 0
// NOTE: Ancillary data not yet captured here due to FSP limitations
#define xgbe_port0_dxio_descriptor { \
.port_present = true, \
.engine_type = ETHERNET_ENGINE, \
.start_logical_lane = 0, \
.end_logical_lane = 0, \
}
/* XGBE ETHERNET PORTS Entry Port 1 */
// XGBE SGMII interface: Physical lane 5, Logical lane 1
// NOTE: Ancillary data not yet captured here due to FSP limitations
#define xgbe_port1_dxio_descriptor { \
.port_present = true, \
.engine_type = ETHERNET_ENGINE, \
.start_logical_lane = 1, \
.end_logical_lane = 1, \
}
static fsp_ddi_descriptor crater_ddi_descriptors[] = {
{ /* DDI0 - DP */
.connector_type = DDI_DP,
@ -103,7 +183,17 @@ void mainboard_get_dxio_ddi_descriptors(
static const fsp_dxio_descriptor crater_dxio_descriptors[] = {
mxm_dxio_descriptor,
ssd_dxio_descriptor
ssd_dxio_descriptor,
tb_dxio_descriptor,
#if CONFIG(ETH_AIC_SLOT_ONLY)
dt_dxio_descriptor, // GPP 0~3
#endif
#if CONFIG(XGBE_WWAN_WLAN)
xgbe_port0_dxio_descriptor, // GPP 0
xgbe_port1_dxio_descriptor, // GPP 1
wwan_dxio_descriptor, // GPP 2
wlan_dxio_descriptor // GPP 3
#endif
};
*dxio_descs = crater_dxio_descriptors;