erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/var/uldrenite: Configure GPP_A16 as NF4

Browse source 
GPP_A16 was wrongly configured to NF2 instead of NF4 i.e. ISH_GP5.
Reference: Intel doc#648094

BUG=b:410645679
TEST=Check GPIO config in the OS.

Change-Id: Ic91ac116513e27992679b0d301afed3bc057bf71
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87444
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yuval Peress <peress@google.com>
This commit is contained in:
Kapil Porwal 2025-04-24 21:44:23 +05:30 • committed by Subrata Banik
commit 6a503fe5a4
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/mainboard/google/brya/variants/uldrenite/gpio.c
View file

@ -35,7 +35,7 @@ static const struct pad_config gpio_table[] = {
/* A15 : USB_OC2# ==> NC */
PAD_NC(GPP_A15, NONE),
/* A16 : ISH_GP5 */
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF4),
/* A17 : GPP_A17 ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
/* A18 : DDSP_HPDB ==> NC */