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payloads/external/edk2: Set StatusD register to work around failing AMD boot

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On recent AMD platforms the VRT bit in the StatusD register is
read-writeable and set every 1024msec when RTC power is good.
This leads to a timeout in RtcWaitToUpdate() waiting for the bit
to be set and the gEfiRealTimeClockArchProtocolGuid won't be installed.
The protocol is critical to boot.

Adjust the code to not clear the VRT bit, as RtcWaitToUpdate() will
return an error, as it assumes the VRT bit is read-only and hardwired
to one as on Intel ICHs. While the timeout could be increased it
would also increase boot time by up to a second.

On platforms where the VRT bit is read-only the introduced code
does the same as before.

Change-Id: I8bc432114c83fa5f5fb35a144e3a35c38ee8a3de
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87415
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Patrick Rudolph 2025-04-22 10:48:00 +02:00 • committed by Matt DeVillier
commit 1044f03878
2 changed files with 7 additions and 0 deletions
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1
payloads/external/Makefile.mk vendored
View file

@ -199,6 +199,7 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
CONFIG_EDK2_UFS_ENABLE=$(CONFIG_EDK2_UFS_ENABLE) \
CONFIG_EDK2_PCO_MMIO_EMMC=$(CONFIG_EDK2_PCO_MMIO_EMMC) \
CONFIG_EDK2_USE_LAPIC_TIMER=$(CONFIG_EDK2_USE_LAPIC_TIMER) \
CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2=$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) \
GCC_CC_x86_32=$(GCC_CC_x86_32) \
GCC_CC_x86_64=$(GCC_CC_x86_64) \
GCC_CC_arm=$(GCC_CC_arm) \

6
payloads/external/edk2/Makefile vendored
View file

@ -115,6 +115,12 @@ endif
ifeq ($(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS), y)
BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport=TRUE
endif
# Preserve VRT bit in RTC_ADDRESS_REGISTER_D
# AMD SoC sets this every 1.024msec, but the generic code assumes it's read-only and
# hardcoded to 1 like on every Intel chipset since Intel ICH.
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2), y)
BUILD_STR += --pcd gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD=0x80
endif
#
# The MrChromebox repository has the following addition options: