Hook up PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUBSTATE to the
option API.
This provides users an easy way to disable power saving options
that can limit performance.
Change-Id: I2b06a7c734a4fd4073e86c668742ee35e1d79956
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81906
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For more than 2 years the option has been unconfigurable.
Since no one seems to have fixed that, the options seems to be
not needed by anyone. So instead of making it configurable now,
we can just as well remove it.
Change-Id: I4055d497c7c23e148d2a09f216c7b910a9b3ea9b
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This patch adds "fatcatnuvo" and "fatcatite" boards to the fatcat
Kconfig.
BUG=b:369728249
TEST=Able to build fatcat/fatcatnuvo/fatcatite and verify the correct
configs selected in coreboot.config
Change-Id: Ice3f1d711426cb356c399de6390fef6f0e6bc748
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84648
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP-S UPDs are programmed according to the configuration (Kconfig and
device tree) in ramstage.
BUG=348678529
TEST=Hardware is programmed as desired and Intel Panther Lake
reference board boots to UI.
Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84552
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The new names include the `AUDIO_` prefix to clearly indicate that
they are audio-related options.
TEST=Able to build google/fatcat w/o any functional impact.
Change-Id: Ia651c19f02423ee214a31168e2bd809e097ce8c2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Remove TODO after checking the addresses are still valid.
source:
PPR 57254 Rev 1.59 Table "Address Space Mapping under APB BUS"
Change-Id: If282ce5687b8a2bdae03ebfc5a37fe5b8b17647a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
HPET and MISC1/2 and registers are used interchangeably in the
datasheets. Add an alias to emphasise that they refer to the same.
source:
PPR #57396 Rev 3.10 Table "ValidValuesTable: PCI interrupt index list"
PPR #57254 Rev 1.59 Table "ValidValuesTable: PCI interrupt index list"
PPR #57396 Rev 3.10 FCH::IO::IntrMisc1Map and FCH::IO::IntrMisc2Map
PPR #57254 Rev 1.59 FCH::IO::IntrMisc1Map and FCH::IO::IntrMisc2Map
Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84574
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per commit 8651731537 ("sconfig: Move config_of_soc from device.h
to static.h"), sources that require access to the devicetree should
directly include static.h so that it can be removed from device.h,
eliminating unnecessary dependencies on static.h for files that only
need the types and function declarations in device.h.
Change-Id: I9db5d80ca0a75ccff3b8e24db0ccbd6b36c84dcb
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add FP enable/disable based on SKU ID for Dratini. This is meant
to resolve a UMA issue with Dratini devices that had the FPMCU
populated on non-fp devices. Since the FPMCU is present, and the
firmware enables the power GPIO's based on variant, not SKU, the
devices were reporting data on fingerprint errantly.
BUG=b:354769653
BUG=b:200825114
TEST=Flash to Dratini, test FP.
Disable test SKU, flash on Dratini, test FP.
To test, run `ectool --name=cros_fp version` in the shell
When enabled, the fpmcu fw version should be displayed.
When disabled, an error should be displayed because the fpmcu
is inaccessible.
Change-Id: Ifc450f51b00b9c3b62268ce94884f5749a3e18c0
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
IORT table represents IO topology of an Arm based system for use
with the Advanced Configuration and Power Interface (ACPI)
Add helper functions for ACPI IORT table for:
1. ITS (Interrupt Translation Service)
2. SMMUV3
3. ID MAP
4. Named Component
5. Root Complex
Based on document: DEN0049E_IO_Remapping_Table_E.e
Change-Id: I7feaf306b5eea21bfc9a2e2a1a2c3ddc3c683c0b
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79404
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes the unnecessary layer provided by soc_info.[hc].
It was providing an abstraction which only was resulting in extra
function calls without any added value as the returned constants are
well identified and could be used directly. More importantly, and this
is the actual selling point in my opinion, this extra indirection was
preventing the compiler from detecting array overflows.
BUG=348678529
TEST=Build is successful
Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6986
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This isn't required by these boards as they both use PTT.
Change-Id: I66b3f614914e51116f3cabe457205fb6b3528387
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84629
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on 24.04, disabling Turbo Boost increases power consumption
which doesn't align with the aim of the Power Saver profile.
Change-Id: I19e8189ee6c44d19bf222c921429284ed1e1aa2a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84628
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on Ubuntu 24.04 by verifying dmesg output and that USB
2.0 and 3.0 devices are registered correctly.
Change-Id: I803a23007f49ea45abc68421e867535081e31b3f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84271
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DPTF is not used on this platform so disable the
PCI device.
Change-Id: I763ab948a79e3a020c1b89c69c714dd0d8f54812
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84270
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
These aren't used so remove them.
Change-Id: I6fd33c5242adb93b1251af9c5b11be3734a7aceb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
MAINBOARD_HAS_TPM2 should only be selected for the boards
that have memory mapped TPMs. The ones that use Intel PTT
don't need it.
Change-Id: I02b5b0912afbd7c4634c208bb17db16d0ac7ba99
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
DPTF is not used on this platform so disable the
PCI device.
Change-Id: I7fa01936568108dd7707a3c2ea7041a1198533b5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84266
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These aren't used so remove them.
Change-Id: I6b9cf29843047bff9a37f82b899ff1d10b206888
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 24.04
No known issues.
https://starlabs.systems/pages/starfighter-specification
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I046e70845a5201d6f6ab062aee91fa8be9728737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
- This patch update the original google/fatcat support added
with Meteor Lake support as a workaround.
- Add initial support to build google/fatcat for Panther Lake SOC
- Add soc acpi file entry in mainboard dsdt.asl
BUG=b:348678529
TEST=Build google fatcat board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83419
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GCC-13 introduced the nullptr constant. Use it when compiling with the
C23 standard.
Change-Id: I07db866bebfd25f1a60d18a3228ada2957500234
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83459
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel TXT SINIT required the D_LCK bit set. Although coreboot
tries to set it, the bit ws still clear. The D_LCK bit has to be
set using I/O CF8/CFC cycle.
TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled
Change-Id: I03aff482b53ab7b0bcaccf18e47ad4c22b53583c
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
For platforms without writable PAM-F segment support (e.g. some
simics virtual platforms), put ROM table pointers (e.g. ACPI/SMBIOS
low pointers) into EBDA.
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Change-Id: I2aac74708279813f9a848044d470fdc980ea4305
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set
the UPD to match this to avoid the connection type being mismatched.
If it's mismatched, the TBT port will timeout.
TEST=Boot starbook/rpl and check TBT 4 dock is correctly identified.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3ab68c01f682723dab39870f0676e59ae3d89add
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77567
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
On GNR, there are CXL Type-3 memory windows covered under TOHM. The
current 4GB to TOHM DRAM reporting doesn't work on GNR.
Use MemoryMapDataHob to add high RAM resources as a generic
mechanism for GNR and previous generation SoCs.
TEST=Build and boot on intel/archercity CRB
TEST=Build and boot on intel/beechnutcity CRB
(with topic:"Xeon6-Basic-Boot")
Change-Id: Ie5fbc5735704d95c7ad50740ff0e35737afdbd80
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84304
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes the following warning with clang (18.1.6):
src/soc/mediatek/mt8196/gpio_eint.c:259:44: error: '_Static_assert' with no message is a C23 extension [-Werror,-Wc23-extensions]
259 | _Static_assert(ARRAY_SIZE(eint_data) == 293);
| ^
|
Change-Id: I934b6d7ee8e8a0c204a4e328331c3ff3cd0f07de
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84618
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The LTE module RW101R-GL provide a hardware pin to enable/disable
WWAN RF function.The function is disabled in default and is
controlled by the AT command.Therefore,set the WWAN_RF_DISABLE
Pin to NC, and it has been pull-high by hardware desgin.
BUG=b:368450447
BRANCH=None
TEST= Build firmware and verify the WWAN on/off function in OS.
Change-Id: I47a28342f67f99c5787077c48a01ddbaa77b5967
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
The method "FUNC" allows 1 argument, so remove the
incorrectly referenced and unused second arguemnt.
This fixes:
ToInteger (Arg1, Local1)
Error 6006 - ^ Method argument is not initialized (Arg1)
Change-Id: If5e402579a2caff169e12253e5d9c2c493902ec7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
QEMU aarch64 boots to payload when compiled with clang.
Change-Id: I940a1ccf5cc4ec7bed5b6c8be92fc47922e1e747
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74501
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clang builds slightly larger binaries so increase the section.
The qcsdi is used for an external blob that is currently not in use so
reducing the size is fine for now.
Change-Id: Ide01233f209613678c5408f1afab19415c1071be
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This change removes the SoC-specific `FSP_STATUS_GLOBAL_RESET_REQUIRED_X`
Kconfigs, as they are no longer necessary for handling FSP global reset
requests.
Previously, these Kconfigs were used to select a specific 32-bit reset
status code. However, with the introduction of FSP 2.4 and 64-bit
interfaces, the global reset status code can now vary between
architectures.
To address this, the FSP driver now sets the `FSP_STATUS_GLOBAL_RESET`
config to a common default value (depending upon most commonly used
global reset status code) based on the interface:
- 0x40000003 for 32-bit FSP interfaces
- 0x4000000000000003 for 64-bit FSP interfaces
This default can be overridden if an FSP implementation uses a
different status code (for example: Apollo Lake selects different FSP
reset status code as 0x40000005).
By removing the SoC-specific configurations, this change simplifies
global reset handling and ensures compatibility across different FSP
versions and platforms.
Below table shows the relationship between Platform, FSP and FSP Global
Reset Status:
+-----------------+--------------+-------------------------+
| Platform | FSP | Global Reset Status |
+-----------------+--------------+-------------------------+
| Alder Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Apollo Lake | 32-bit | 0x40000005 |
+-----------------+--------------+-------------------------+
| Cannon Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Elkhart Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Jasper Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Meteor Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Sky Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Tiger Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Panther Lake | 64-bit | 0x4000000000000003 |
+-----------------+--------------+-------------------------+
BUG=b:347669091
TEST=Verified FSP requested global reset functionality on google/rex0
(32-bit) and google/rex64 (64-bit) platforms.
w/ 32-bit FSP:
```
(Wdt) AllowKnownReset
[FspResetSystem2] FSP Reset Initiated
FSP returning control to Bootloader with reset required return status
40000003
FSPS, status=0x40000003
FSP: handling reset type, status=0x40000003
GLOBAL RESET!
global_reset() called!
HECI: Global Reset(Type:1) Command
```
w/ 64-bit FSP:
```
(Wdt) AllowKnownReset
[FspResetSystem2] FSP Reset Initiated
FSP returning control to Bootloader with reset required return status 3
FSPS, status=0x4000000000000003
FSP: handling reset type, status=0x4000000000000003
GLOBAL RESET!
global_reset() called!
HECI: Global Reset(Type:1) Command
```
Change-Id: I32bdbf7ea6afa7d5e5f91ea96d887719d26a593f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84572
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
The `fsp_get_pch_reset_status()` function returns a FSP reset status
code. This change corrects its return type from `uint32_t` to
`efi_return_status_t` to ensure consistency with the FSP API and
prevent potential issues caused by type mismatch.
This correction is necessary for compatibility with both 32-bit and
64-bit FSP interfaces. The change also updates all callers of this
function in the Meteor Lake and Panther Lake SoCs to use the correct
return type.
Includes `fsp/api.h` to provide the `efi_return_status_t` definition.
BUG=b:347669091
TEST=Verified global reset functionality on google/rex0 (32-bit) and
google/rex64 (64-bit) platforms.
Change-Id: I0cdee541506bf424f50fd00833d5ee200a3a8a48
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84571
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a Power Resource for Intel Bluetooth, that can reset
the Bluetooth using the delay configured in the DSM.
Change-Id: I3b25fd180e21100e3cb001fc6ba0da7f47b2ad12
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84146
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add "CNMT" Mutex, that will be used by the Bluetooth and CNVi
driver.
Change-Id: I607865458f925d6f4aa713e07cfa34e83b2e5c8f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84598
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It should be in HEX.
Change-Id: I15a354bae414ad94a2f76030b3099179022b935c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84546
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The platform uses eSPI so these are not needed.
Change-Id: I507aa59fcf2540ae6170896a51aa952f5e73eee8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83691
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SMMSTORE to the default FMAP to allow using UefiPayload on
this board that requires a non-volatile variable store.
TEST: Booted an UEFI compatible OS using EDK2 as payload.
Change-Id: I32fb0a882c62e42da9f3caec54f8d33333fc8598
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84559
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
