soc/intel: Deprecate SoC-specific global reset status configs

This change removes the SoC-specific `FSP_STATUS_GLOBAL_RESET_REQUIRED_X`
Kconfigs, as they are no longer necessary for handling FSP global reset
requests.

Previously, these Kconfigs were used to select a specific 32-bit reset
status code. However, with the introduction of FSP 2.4 and 64-bit
interfaces, the global reset status code can now vary between
architectures.

To address this, the FSP driver now sets the `FSP_STATUS_GLOBAL_RESET`
config to a common default value (depending upon most commonly used
global reset status code) based on the interface:
- 0x40000003 for 32-bit FSP interfaces
- 0x4000000000000003 for 64-bit FSP interfaces

This default can be overridden if an FSP implementation uses a
different status code (for example: Apollo Lake selects different FSP
reset status code as 0x40000005).

By removing the SoC-specific configurations, this change simplifies
global reset handling and ensures compatibility across different FSP
versions and platforms.

Below table shows the relationship between Platform, FSP and FSP Global
Reset Status:
+-----------------+--------------+-------------------------+
| Platform        |  FSP         |    Global Reset Status  |
+-----------------+--------------+-------------------------+
| Alder Lake      |  32-bit      |    0x40000003           |
+-----------------+--------------+-------------------------+
| Apollo Lake     |  32-bit      |    0x40000005           |
+-----------------+--------------+-------------------------+
| Cannon Lake     |  32-bit      |    0x40000003           |
+-----------------+--------------+-------------------------+
| Elkhart Lake    |  32-bit      |    0x40000003           |
+-----------------+--------------+-------------------------+
| Jasper Lake     |  32-bit      |    0x40000003           |
+-----------------+--------------+-------------------------+
| Meteor Lake     |  32-bit      |    0x40000003           |
+-----------------+--------------+-------------------------+
| Sky Lake        |  32-bit      |    0x40000003           |
+-----------------+--------------+-------------------------+
| Tiger Lake      |  32-bit      |    0x40000003           |
+-----------------+--------------+-------------------------+
| Panther Lake    |  64-bit      |    0x4000000000000003   |
+-----------------+--------------+-------------------------+

BUG=b:347669091
TEST=Verified FSP requested global reset functionality on google/rex0
(32-bit) and google/rex64 (64-bit) platforms.

w/ 32-bit FSP:

```
(Wdt) AllowKnownReset
[FspResetSystem2] FSP Reset Initiated
FSP returning control to Bootloader with reset required return status
40000003
FSPS, status=0x40000003
FSP: handling reset type, status=0x40000003
GLOBAL RESET!
global_reset() called!
HECI: Global Reset(Type:1) Command
```

w/ 64-bit FSP:

```
(Wdt) AllowKnownReset
[FspResetSystem2] FSP Reset Initiated
FSP returning control to Bootloader with reset required return status 3
FSPS, status=0x4000000000000003
FSP: handling reset type, status=0x4000000000000003
GLOBAL RESET!
global_reset() called!
HECI: Global Reset(Type:1) Command
```

Change-Id: I32bdbf7ea6afa7d5e5f91ea96d887719d26a593f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84572
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>

src/drivers/intel/fsp2_0/Kconfig

@@ -341,50 +341,32 @@ config FSP_M_ADDR
 	help
 	  The address FSP-M will be relocated to during build time
 
-config FSP_STATUS_GLOBAL_RESET_REQUIRED_3
-	bool
-	help
-	  FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
-
-config FSP_STATUS_GLOBAL_RESET_REQUIRED_4
-	bool
-	help
-	  FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
-
-config FSP_STATUS_GLOBAL_RESET_REQUIRED_5
-	bool
-	help
-	  FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
-
-config FSP_STATUS_GLOBAL_RESET_REQUIRED_6
-	bool
-	help
-	  FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
-
-config FSP_STATUS_GLOBAL_RESET_REQUIRED_7
-	bool
-	help
-	  FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
-
-config FSP_STATUS_GLOBAL_RESET_REQUIRED_8
-	bool
-	help
-	  FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
-
 config FSP_STATUS_GLOBAL_RESET
 	hex
 	depends on SOC_INTEL_COMMON_FSP_RESET
-	default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3
-	default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4
-	default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5
-	default 0x40000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6
-	default 0x40000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7
-	default 0x40000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8
-	default 0xffffffff
+	range 0x4000000000000003 0x4000000000000008 if !PLATFORM_USES_FSP2_X86_32
+	range 0x40000003 0x40000008
+	default 0x4000000000000003 if !PLATFORM_USES_FSP2_X86_32
+	default 0x40000003
 	help
 	  If global reset is supported by SoC then select the correct status value for global
-	  reset type from SoC Kconfig based on available Kconfig options
-	  FSP_STATUS_GLOBAL_RESET_REQUIRED_X. Default is unsupported.
+	  reset type.
+
+	  This option specifies the global reset status code used by the
+	  platform, as defined in the FSP specification.
+
+	  The FSP specification allows for a range of values to indicate a
+	  global reset request, typically between
+	  FSP_STATUS_GLOBAL_RESET_REQUIRED_3 and
+	  FSP_STATUS_GLOBAL_RESET_REQUIRED_8.
+
+	  This option defaults to the most commonly used global reset
+	  status code in FSP implementations:
+	  - 0x40000003 for 32-bit FSP interfaces
+	  - 0x4000000000000003 for 64-bit FSP interfaces
+
+	  If your FSP implementation uses a different global reset status
+	  code, override this default value accordingly.
 
 config SOC_INTEL_COMMON_FSP_RESET
 	bool

src/soc/intel/alderlake/Kconfig

@@ -18,7 +18,6 @@ config SOC_INTEL_ALDERLAKE
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
 	select FSP_M_XIP
 	select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN
-	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	select FSP_USES_CB_DEBUG_EVENT_HANDLER
 	select FSPS_HAS_ARCH_UPD
 	select GENERIC_GPIO_LIB

src/soc/intel/apollolake/Kconfig

@@ -21,7 +21,6 @@ config SOC_INTEL_APOLLOLAKE
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FAST_SPI_GENERATE_SSDT
 	select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
-	select FSP_STATUS_GLOBAL_RESET_REQUIRED_5
 	select GENERIC_GPIO_LIB
 	select HAVE_ASAN_IN_ROMSTAGE
 	select HAVE_CF9_RESET_PREPARE
@@ -102,6 +101,10 @@ config SOC_INTEL_GEMINILAKE
 
 if SOC_INTEL_APOLLOLAKE
 
+config FSP_STATUS_GLOBAL_RESET
+	hex
+	default 0x40000005
+
 config USE_LEGACY_8254_TIMER
 	default y
 

src/soc/intel/cannonlake/Kconfig

@@ -15,7 +15,6 @@ config SOC_INTEL_CANNONLAKE_BASE
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_COMPRESS_FSP_S_LZMA
 	select FSP_M_XIP
-	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	select FSP_USES_CB_STACK
 	select GENERIC_GPIO_LIB
 	select HAVE_DPTF_EISA_HID

src/soc/intel/elkhartlake/Kconfig

@@ -13,7 +13,6 @@ config SOC_INTEL_ELKHARTLAKE
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
-	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
 	select HAVE_SMI_HANDLER

src/soc/intel/jasperlake/Kconfig

@@ -14,7 +14,6 @@ config SOC_INTEL_JASPERLAKE
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
-	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	select GENERIC_GPIO_LIB
 	select HAVE_DPTF_EISA_HID
 	select HAVE_FSP_GOP

src/soc/intel/meteorlake/Kconfig

@@ -19,7 +19,6 @@ config SOC_INTEL_METEORLAKE
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
 	select FSP_M_XIP
-	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE if !SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON
 	select FSP_USES_CB_DEBUG_EVENT_HANDLER
 	select FSPS_HAS_ARCH_UPD

src/soc/intel/pantherlake/Kconfig

@@ -17,7 +17,6 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
-	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	select FSP_UGOP_EARLY_SIGN_OF_LIFE
 	select FSP_USES_CB_DEBUG_EVENT_HANDLER
 	select FSPS_HAS_ARCH_UPD

src/soc/intel/skylake/Kconfig

@@ -13,7 +13,6 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
-	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
 	select HAVE_FSP_LOGO_SUPPORT

src/soc/intel/tigerlake/Kconfig

@@ -17,7 +17,6 @@ config SOC_INTEL_TIGERLAKE
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
 	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_M_XIP
-	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
 	select HAVE_HYPERTHREADING