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soc/amd/.../amd_pci_int_defs.h: Update according to datasheet

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HPET and MISC1/2 and registers are used interchangeably in the
datasheets. Add an alias to emphasise that they refer to the same.

source:
PPR #57396 Rev 3.10 Table "ValidValuesTable: PCI interrupt index list"
PPR #57254 Rev 1.59 Table "ValidValuesTable: PCI interrupt index list"
PPR #57396 Rev 3.10 FCH::IO::IntrMisc1Map and FCH::IO::IntrMisc2Map
PPR #57254 Rev 1.59 FCH::IO::IntrMisc1Map and FCH::IO::IntrMisc2Map

Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84574
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maximilian Brune 2024-10-01 12:33:09 +02:00 • committed by Marshall Dawson
commit 3c11347f7c
2 changed files with 8 additions and 4 deletions
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6
src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
View file

@ -21,8 +21,10 @@
#define PIRQ_H 0x07 /* INT H */
#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */
#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */
#define PIRQ_HPET_L 0x0a /* HPET TMR{0..2}_CONF_CAP_H[0:7] */
#define PIRQ_HPET_H 0x0b /* HPET TMR{0..2}_CONF_CAP_H[15:8] */
#define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */
#define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */
#define PIRQ_HPET_L PIRQ_MISC1 /* HPET TMR{0..2}_CONF_CAP_L[0:7] */
#define PIRQ_HPET_H PIRQ_MISC2 /* HPET TMR{0..2}_CONF_CAP_H[15:8] */
#define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */
#define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */
#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */

6
src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h
View file

@ -19,8 +19,10 @@
#define PIRQ_H 0x07 /* INT H */
#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */
#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */
#define PIRQ_HPET_L 0x0a /* HPET TMR{0..2}_CONF_CAP_H[0:7] */
#define PIRQ_HPET_H 0x0b /* HPET TMR{0..2}_CONF_CAP_H[15:8] */
#define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */
#define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */
#define PIRQ_HPET_L PIRQ_MISC1 /* HPET TMR{0..2}_CONF_CAP_L[0:7] */
#define PIRQ_HPET_H PIRQ_MISC2 /* HPET TMR{0..2}_CONF_CAP_H[15:8] */
#define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */
#define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */
#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */