mb/google/fatcat: Add Panther Lake SOC support
- This patch update the original google/fatcat support added with Meteor Lake support as a workaround. - Add initial support to build google/fatcat for Panther Lake SOC - Add soc acpi file entry in mainboard dsdt.asl BUG=b:348678529 TEST=Build google fatcat board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83419 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Saurabh Mishra
Subrata Banik
parent
6042ba010a
commit
362cc976fb
5 changed files with 117 additions and 16 deletions
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@ -3,36 +3,51 @@
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config BOARD_GOOGLE_FATCAT_COMMON
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_MIPI_CAMERA
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select DRIVERS_INTEL_PMC
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select DRIVERS_INTEL_SOUNDWIRE
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select DRIVERS_SOUNDWIRE_ALC722
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select DRIVERS_SPI_ACPI
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select DUMP_SMBIOS_TYPE17
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select EC_ACPI
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_GOOGLE_CHROMEEC_ESPI
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select EC_GOOGLE_CHROMEEC_MEC
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select EC_GOOGLE_CHROMEEC_SKUID
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select FW_CONFIG
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select FW_CONFIG_SOURCE_CHROMEEC_CBI
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select GENERATE_SMBIOS_TABLES
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select GOOGLE_SMBIOS_MAINBOARD_VERSION
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_SPD_IN_CBFS
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select I2C_TPM
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_DISABLE_STAGE_CACHE
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_USES_IFD_EC_REGION
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select MB_COMPRESS_RAMSTAGE_LZ4
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select PMC_IPC_ACPI_INTERFACE
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select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
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select SOC_INTEL_CSE_LITE_SKU
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select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2
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select SOC_INTEL_CSE_SEND_EOP_ASYNC
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select SOC_INTEL_PANTHERLAKE_U_H
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select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
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config BOARD_GOOGLE_BASEBOARD_FATCAT
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def_bool n
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select BOARD_GOOGLE_FATCAT_COMMON
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select CHROMEOS_WIFI_SAR if CHROMEOS
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select DRIVERS_INTEL_USB4_RETIMER
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select HAVE_SLP_S0_GATE
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select MAINBOARD_HAS_CHROMEOS
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select MEMORY_SOLDERDOWN
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_IOE_DIE_SUPPORT
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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select SYSTEM_TYPE_LAPTOP
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select TPM_GOOGLE_TI50
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@ -42,8 +57,6 @@ config BOARD_GOOGLE_MODEL_FATCAT
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config BOARD_GOOGLE_FATCAT
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select BOARD_GOOGLE_MODEL_FATCAT
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select HAVE_X86_64_SUPPORT
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select USE_X86_64_SUPPORT
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if BOARD_GOOGLE_FATCAT_COMMON
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@ -53,8 +66,8 @@ config BASEBOARD_DIR
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config CHROMEOS
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_MANUAL_RECOVERY
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select HAS_RECOVERY_MRC_CACHE
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@ -72,14 +85,13 @@ config DEVICETREE
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config DIMM_SPD_SIZE
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default 512
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# FIXME: update below code as per board schematics
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config DRIVER_TPM_I2C_ADDR
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hex
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default 0x0
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default 0x50
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x0
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default 0x03
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP
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@ -103,13 +115,9 @@ config MEMORY_SOLDERDOWN
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select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
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select HAVE_SPD_IN_CBFS
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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# FIXME: update as per board schematics
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 0
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default 47 # GPE0_DW1_15 (GPP_D15)
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# FIXME: update as per board schematics
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config UART_FOR_CONSOLE
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@ -123,6 +131,9 @@ config VARIANT_DIR
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string
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default "fatcat" if BOARD_GOOGLE_MODEL_FATCAT
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config VBOOT
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select VBOOT_LID_SWITCH
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@ -2,6 +2,7 @@
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#include <acpi/acpi.h>
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#include <variant/ec.h>
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#include <variant/gpio.h>
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DefinitionBlock(
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"dsdt.aml",
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@ -9,8 +10,33 @@ DefinitionBlock(
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725
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0x20240917
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)
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{
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/* TODO: Add ACPI code as per board design */
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#include <acpi/dsdt_top.asl>
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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/* global NVS and variables */
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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Device (\_SB.PCI0) {
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/pantherlake/acpi/southbridge.asl>
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#include <soc/intel/pantherlake/acpi/tcss.asl>
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}
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#if CONFIG(EC_GOOGLE_CHROMEEC)
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/* ChromeOS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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#endif
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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@ -21,7 +21,7 @@ void mainboard_update_soc_chip_config(struct soc_intel_pantherlake_config *confi
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variant_update_soc_chip_config(config);
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}
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__weak void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
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void __weak variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
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{
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/* default implementation does nothing */
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}
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@ -1,3 +1,65 @@
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chip soc/intel/pantherlake
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device domain 0 on end
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# GPE configuration
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register "pmc_gpe0_dw0" = "GPP_A"
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register "pmc_gpe0_dw1" = "GPP_D"
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register "pmc_gpe0_dw2" = "GPP_E"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0
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register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1
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register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2
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register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3
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register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4
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register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5
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register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6
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register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7
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register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0
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register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 1
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register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0
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register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1
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register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2
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register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3
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# Enable s0ix
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register "s0ix_enable" = "false"
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# DPTF enable
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register "dptf_enable" = "false"
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# Enable CNVi BT
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register "cnvi_bt_core" = "true"
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register "serial_io_uart_mode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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register "pch_hda_dsp_enable" = "true"
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register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
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register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
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register "pch_hda_idisp_codec_enable" = "true"
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register "pch_hda_sdi_enable" = "{ true, false }"
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device domain 0 on
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device ref igpu on end
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device ref dtt on end
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device ref npu on end
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device ref xhci on end
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device ref pmc_shared_sram on end
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device ref heci1 on end
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device ref uart0 on end
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device ref soc_espi on
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end
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end
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end
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@ -6,5 +6,7 @@
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#include <baseboard/gpio.h>
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/* TODO: Add GPIO as per fatcat board */
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/* Dummy pin number for ACPI table to build */
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#define GPE_EC_WAKE 0
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#endif /* __MAINBOARD_GPIO_H__ */
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