mb/starlabs/starfighter: Add Raptor Lake StarFighter Mk I variant
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Windows 11 * Ubuntu 24.04 No known issues. https://starlabs.systems/pages/starfighter-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I046e70845a5201d6f6ab062aee91fa8be9728737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes
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32 changed files with 1837 additions and 0 deletions
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@ -334,6 +334,7 @@ StarLite Mk V <starlabs/lite_adl.md>
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StarBook Mk V <starlabs/starbook_tgl.md>
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StarBook Mk VI <starlabs/starbook_adl.md>
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Byte Mk II <starlabs/byte_adl.md>
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StarFighter Mk I <starlabs/starfighter_rpl.md>
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Flashing devices <starlabs/common/flashing.md>
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```
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91
Documentation/mainboard/starlabs/starfighter_rpl.md
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91
Documentation/mainboard/starlabs/starfighter_rpl.md
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@ -0,0 +1,91 @@
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# StarFighter Mk I
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## Specs
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- CPU (full processor specs available at https://ark.intel.com)
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- Intel i3-1315U (Raptor Lake)
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- Intel i7-13700H (Raptor Lake)
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- Intel i9-13900H (Raptor Lake)
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- EC
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- ITE IT5570E
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- Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
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- Battery
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- USB-C PD Charger
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- Suspend / resume
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- GPU
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- Intel® Iris® Xe Graphics
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- GOP driver is recommended, VBT is provided
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- eDP 16-inch 3840x2400 or 2560x1600 LCD
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- HDMI video
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- USB-C DisplayPort video
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- Memory
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- 16, 32 or 64GB LPDDR5 on-board memory
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- Networking
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- AX210 2230 WiFi / Bluetooth
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- Sound
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- Realtek ALC256
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- Internal speakers
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- Removable microphone
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- Combined headphone / microphone 3.5-mm jack
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- HDMI audio
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- USB-C DisplayPort audio
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- Storage
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- 2 xM.2 PCIe SSD
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- RTS5129 MicroSD card reader
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- USB
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- 1920x1080 removable CCD camera
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- 2 x Thunderbolt 4.0 (left) (Raptor Lake)
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- USB 3.1 Gen 2 Type-A (left)
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- USB 3.1 Gen 2 Type-A (right)
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- USB 3.1 Gen 1 Type-A (right)
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## Building coreboot
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Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starfighter_rpl` as config file.
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### Preliminaries
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Prior to building coreboot the following files are required:
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* Intel Flash Descriptor file (descriptor.bin)
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* Intel Management Engine firmware (me.bin)
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* ITE Embedded Controller firmware (ec.bin)
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The files listed below are optional:
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- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
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These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
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### Build
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The following commands will build a working image:
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```bash
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make distclean
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make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starfighter_rpl
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make
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```
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## Flashing coreboot
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```{eval-rst}
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+---------------------+------------+
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| Type | Value |
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+=====================+============+
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| Socketed flash | no |
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+---------------------+------------+
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| Vendor | Winbond |
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+---------------------+------------+
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| Model | W25Q256.V |
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+---------------------+------------+
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| Size | 32 MiB |
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+---------------------+------------+
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| Package | SOIC-8 |
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+---------------------+------------+
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| Internal flashing | yes |
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+---------------------+------------+
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| External flashing | yes |
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+---------------------+------------+
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```
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Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
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131
src/mainboard/starlabs/starfighter/Kconfig
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131
src/mainboard/starlabs/starfighter/Kconfig
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@ -0,0 +1,131 @@
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## SPDX-License-Identifier: GPL-2.0-only
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config BOARD_STARLABS_STARFIGHTER_SERIES
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_INTEL_PMC
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select DRIVERS_INTEL_USB4_RETIMER
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select DRIVERS_I2C_HID
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select EC_STARLABS_FAN
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select EC_STARLABS_ITE
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select EC_STARLABS_KBL_LEVELS
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select EC_STARLABS_MAX_CHARGE
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select EC_STARLABS_MERLIN
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select EC_STARLABS_NEED_ITE_BIN
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select HAVE_SPD_IN_CBFS
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_TPM2
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select MEMORY_MAPPED_TPM
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select NO_UART_ON_SUPERIO
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select SOC_INTEL_ALDERLAKE
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select SOC_INTEL_ALDERLAKE_PCH_P
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_COMMON_BLOCK_TCSS
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select SOC_INTEL_CRASHLOG
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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select SOC_INTEL_RAPTORLAKE
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select SPI_FLASH_WINBOND
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select SYSTEM_TYPE_LAPTOP
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select TPM_MEASURED_BOOT
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select VALIDATE_INTEL_DESCRIPTOR
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config BOARD_STARLABS_STARFIGHTER_RPL
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select BOARD_STARLABS_STARFIGHTER_SERIES
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if BOARD_STARLABS_STARFIGHTER_SERIES
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config CCD_PORT
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int
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default 3 # TODO
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config CONSOLE_SERIAL
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default n if !EDK2_DEBUG
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config D3COLD_SUPPORT
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default n
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config DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config DIMM_SPD_SIZE
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default 512
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config DRIVER_TPM_SPI_CHIP
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default 2
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config EC_GPE_SCI
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default 0x6e
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config EC_STARLABS_ADD_ITE_BIN
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default n
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config EC_STARLABS_BATTERY_MODEL
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default "AEC617573-4S1P"
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config EC_STARLABS_BATTERY_TYPE
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default "LION"
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config EC_STARLABS_BATTERY_OEM
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default "Apower Electronics"
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config EC_STARLABS_ITE_BIN_PATH
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string
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depends on EC_STARLABS_NEED_ITE_BIN
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default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
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config EC_VARIANT_DIR
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default "merlin"
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config EDK2_BOOTSPLASH_FILE
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string
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default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/vboot.fmd" if VBOOT
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
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config IFD_BIN_PATH
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string
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default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashdescriptor.bin"
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config MAINBOARD_DIR
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default "starlabs/starfighter"
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config MAINBOARD_FAMILY
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string
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default "F1"
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config MAINBOARD_PART_NUMBER
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default "StarFighter Mk I"
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "StarFighter"
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config ME_BIN_PATH
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# string
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default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin"
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config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
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default n
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config SOC_INTEL_CSE_SEND_EOP_EARLY
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default n
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config UART_FOR_CONSOLE
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default 0
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config USE_PM_ACPI_TIMER
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default n
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config VBOOT
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select VBOOT_VBNV_FLASH
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config VARIANT_DIR
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default "rpl"
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endif
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6
src/mainboard/starlabs/starfighter/Kconfig.name
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6
src/mainboard/starlabs/starfighter/Kconfig.name
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@ -0,0 +1,6 @@
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## SPDX-License-Identifier: GPL-2.0-only
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comment "Star Labs StarFighter Series"
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config BOARD_STARLABS_STARFIGHTER_RPL
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bool "Star Labs StarFighter Mk I (i3-1315U, i7-13700H and i9-13900H)"
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12
src/mainboard/starlabs/starfighter/Makefile.mk
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12
src/mainboard/starlabs/starfighter/Makefile.mk
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## SPDX-License-Identifier: GPL-2.0-only
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += ./spd
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subdirs-y += variants/$(VARIANT_DIR)
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bootblock-y += bootblock.c
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ramstage-y += hda_verb.c
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ramstage-y += mainboard.c
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ramstage-y += smbios.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
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1
src/mainboard/starlabs/starfighter/acpi/ec.asl
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1
src/mainboard/starlabs/starfighter/acpi/ec.asl
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@ -0,0 +1 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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5
src/mainboard/starlabs/starfighter/acpi/mainboard.asl
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5
src/mainboard/starlabs/starfighter/acpi/mainboard.asl
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/* SPDX-License-Identifier: GPL-2.0-only */
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Scope (\_SB) {
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#include "sleep.asl"
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}
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11
src/mainboard/starlabs/starfighter/acpi/sleep.asl
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11
src/mainboard/starlabs/starfighter/acpi/sleep.asl
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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Method (MPTS, 1, NotSerialized)
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{
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RPTS (Arg0)
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}
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Method (MWAK, 1, NotSerialized)
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{
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RWAK (Arg0)
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}
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1
src/mainboard/starlabs/starfighter/acpi/superio.asl
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1
src/mainboard/starlabs/starfighter/acpi/superio.asl
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@ -0,0 +1 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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6
src/mainboard/starlabs/starfighter/board_info.txt
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6
src/mainboard/starlabs/starfighter/board_info.txt
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Vendor name: Star Labs
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Board name: StarFighter
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Category: laptop
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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14
src/mainboard/starlabs/starfighter/bootblock.c
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14
src/mainboard/starlabs/starfighter/bootblock.c
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@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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#include <variants.h>
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void bootblock_mainboard_init(void)
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{
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const struct pad_config *pads;
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size_t num;
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pads = variant_early_gpio_table(&num);
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gpio_configure_pads(pads, num);
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}
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25
src/mainboard/starlabs/starfighter/cmos.default
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25
src/mainboard/starlabs/starfighter/cmos.default
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## SPDX-License-Identifier: GPL-2.0-only
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# hardcoded
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boot_option=Fallback
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# console
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debug_level=Debug
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# cpu
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hyper_threading=Enable
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vtd=Enable
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power_profile=Balanced
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me_state=Disable
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# Devices
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wireless=Enable
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webcam=Enable
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microphone=Enable
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pci_hot_plug=Disable
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# EC
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kbl_timeout=30 seconds
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fn_ctrl_swap=Disable
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# southbridge
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power_on_after_fail=Disable
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# Functions
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fn_lock_state=0x1
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trackpad_state=0x1
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kbl_brightness=0x0
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kbl_state=0x1
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107
src/mainboard/starlabs/starfighter/cmos.layout
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107
src/mainboard/starlabs/starfighter/cmos.layout
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@ -0,0 +1,107 @@
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# SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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# Bank: 1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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# -----------------------------------------------------------------
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# coreboot config options: ramtop
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304 80 h 0 ramtop
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 2 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 3 debug_level
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# coreboot config options: cpu
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#400 8 r 0 reserved for century byte
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408 1 e 1 hyper_threading
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416 1 e 1 vtd
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424 2 e 7 power_profile
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432 1 e 5 me_state
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440 4 h 0 me_state_counter
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# coreboot config options: Devices
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504 1 e 1 wireless
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512 1 e 1 webcam
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520 1 e 1 microphone
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# coreboot config options: EC
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600 3 e 4 kbl_timeout
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608 1 e 1 fn_ctrl_swap
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616 2 e 8 max_charge
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624 2 e 9 fan_mode
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# coreboot config options: southbridge
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800 2 e 6 power_on_after_fail
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# Bank: 2
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# embedded controller settings (outside the checksummed area)
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1024 8 h 1 fn_lock_state
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1032 8 h 1 trackpad_state
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1040 8 h 10 kbl_brightness
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1048 8 h 1 kbl_state
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Fallback
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2 1 Normal
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3 0 Emergency
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3 1 Alert
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3 2 Critical
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3 3 Error
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3 4 Warning
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3 5 Notice
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3 6 Info
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3 7 Debug
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3 8 Spew
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4 0 30 seconds
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4 1 1 minute
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4 2 3 minutes
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4 3 5 minutes
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4 4 Never
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5 0 Enable
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5 1 Disable
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6 0 Disable
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6 1 Enable
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6 2 Keep
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7 0 Power Saver
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7 1 Balanced
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7 2 Performance
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8 0 100%
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8 1 80%
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8 2 60%
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9 0 Normal
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9 1 Aggressive
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9 2 Quiet
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10 0 Off
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10 1 Low
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10 2 High
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10 3 On
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# -----------------------------------------------------------------
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checksums
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checksum 392 983 984
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46
src/mainboard/starlabs/starfighter/dsdt.asl
Normal file
46
src/mainboard/starlabs/starfighter/dsdt.asl
Normal file
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@ -0,0 +1,46 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20220930
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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Device (\_SB.PCI0)
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/alderlake/acpi/southbridge.asl>
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#include <soc/intel/alderlake/acpi/tcss.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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#include <soc/intel/common/block/acpi/acpi/gna.asl>
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||||
|
||||
/* PS/2 Keyboard */
|
||||
#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
/* Star Labs EC */
|
||||
#include <ec/starlabs/merlin/acpi/ec.asl>
|
||||
|
||||
Scope (\_SB)
|
||||
{
|
||||
/* HID Driver */
|
||||
#include <ec/starlabs/merlin/acpi/hid.asl>
|
||||
|
||||
/* Suspend Methods */
|
||||
#include <ec/starlabs/merlin/acpi/suspend.asl>
|
||||
}
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
26
src/mainboard/starlabs/starfighter/hda_verb.c
Normal file
26
src/mainboard/starlabs/starfighter/hda_verb.c
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/azalia_device.h>
|
||||
#include <option.h>
|
||||
#include <types.h>
|
||||
|
||||
#define AZALIA_CODEC_ALC256 0x10ec0256
|
||||
|
||||
static const u32 override_verb[] = {
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
|
||||
};
|
||||
|
||||
static void disable_microphone(u8 *base)
|
||||
{
|
||||
azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb));
|
||||
}
|
||||
|
||||
void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
|
||||
{
|
||||
if (viddid == AZALIA_CODEC_ALC256) {
|
||||
printk(BIOS_DEBUG, "CMOS: viddid = %08x\n", viddid);
|
||||
if (get_uint_option("microphone", 1) == 0)
|
||||
disable_microphone(base);
|
||||
}
|
||||
}
|
||||
26
src/mainboard/starlabs/starfighter/include/variants.h
Normal file
26
src/mainboard/starlabs/starfighter/include/variants.h
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _BASEBOARD_VARIANTS_H_
|
||||
#define _BASEBOARD_VARIANTS_H_
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
enum cmos_power_profile {
|
||||
PP_POWER_SAVER = 0,
|
||||
PP_BALANCED = 1,
|
||||
PP_PERFORMANCE = 2,
|
||||
};
|
||||
#define NUM_POWER_PROFILES 3
|
||||
|
||||
enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback);
|
||||
|
||||
/*
|
||||
* The next set of functions return the gpio table and fill in the number of
|
||||
* entries for each table.
|
||||
*/
|
||||
const struct pad_config *variant_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num);
|
||||
|
||||
void devtree_update(void);
|
||||
|
||||
#endif /* _BASEBOARD_VARIANTS_H_ */
|
||||
27
src/mainboard/starlabs/starfighter/mainboard.c
Normal file
27
src/mainboard/starlabs/starfighter/mainboard.c
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <option.h>
|
||||
#include <variants.h>
|
||||
|
||||
enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback)
|
||||
{
|
||||
const unsigned int power_profile = get_uint_option("power_profile", fallback);
|
||||
return power_profile < NUM_POWER_PROFILES ? power_profile : fallback;
|
||||
}
|
||||
|
||||
static void init_mainboard(void *chip_info)
|
||||
{
|
||||
const struct pad_config *pads;
|
||||
size_t num;
|
||||
|
||||
pads = variant_gpio_table(&num);
|
||||
gpio_configure_pads(pads, num);
|
||||
|
||||
devtree_update();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.init = init_mainboard,
|
||||
};
|
||||
39
src/mainboard/starlabs/starfighter/smbios.c
Normal file
39
src/mainboard/starlabs/starfighter/smbios.c
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <chip.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <ec/starlabs/merlin/ec.h>
|
||||
#include <smbios.h>
|
||||
#include <types.h>
|
||||
#include <uuid.h>
|
||||
#include <variants.h>
|
||||
|
||||
/* Get the Embedded Controller firmware version */
|
||||
void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision)
|
||||
{
|
||||
u16 ec_version = ec_get_version();
|
||||
|
||||
*ec_major_revision = ec_version >> 8;
|
||||
*ec_minor_revision = ec_version & 0xff;
|
||||
}
|
||||
|
||||
const char *smbios_system_sku(void)
|
||||
{
|
||||
return CONFIG_MAINBOARD_FAMILY;
|
||||
}
|
||||
|
||||
u8 smbios_mainboard_feature_flags(void)
|
||||
{
|
||||
return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
|
||||
}
|
||||
|
||||
const char *smbios_chassis_version(void)
|
||||
{
|
||||
return smbios_mainboard_version();
|
||||
}
|
||||
|
||||
const char *smbios_chassis_serial_number(void)
|
||||
{
|
||||
return smbios_mainboard_serial_number();
|
||||
}
|
||||
32
src/mainboard/starlabs/starfighter/spd/16gb.spd.hex
Normal file
32
src/mainboard/starlabs/starfighter/spd/16gb.spd.hex
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00
|
||||
48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0
|
||||
03 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
|
||||
16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C 00 00 00 00 00 7F 00 69 9A
|
||||
11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
|
||||
34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
|
||||
45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
32
src/mainboard/starlabs/starfighter/spd/32gb.spd.hex
Normal file
32
src/mainboard/starlabs/starfighter/spd/32gb.spd.hex
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
23 10 13 0E 16 22 B5 08 00 40 00 00 0A 01 00 00
|
||||
48 00 0A FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
|
||||
04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
|
||||
16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C 00 00 00 00 00 7F 00 69 9A
|
||||
11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
|
||||
34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
|
||||
45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
32
src/mainboard/starlabs/starfighter/spd/64gb.spd.hex
Normal file
32
src/mainboard/starlabs/starfighter/spd/64gb.spd.hex
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
23 10 15 0E 16 2A F9 08 00 40 00 00 09 01 00 00
|
||||
48 00 08 FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
|
||||
04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 16 36 16 36
|
||||
16 36 16 36 00 00 16 36 16 36 16 36 16 36 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C 00 00 00 00 00 7F 43 69 9A
|
||||
11 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 D8 53
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 2C 25 20 02 F0 E6 A8 9B 38 41 54 46 31 47 36
|
||||
34 41 5A 2D 33 47 32 45 31 20 20 20 20 31 80 2C
|
||||
45 48 4D 30 30 30 30 33 37 30 33 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
5
src/mainboard/starlabs/starfighter/spd/Makefile.mk
Normal file
5
src/mainboard/starlabs/starfighter/spd/Makefile.mk
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
SPD_SOURCES = 16gb # 13
|
||||
SPD_SOURCES += 32gb # 0
|
||||
SPD_SOURCES += 64gb # 8
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
bootblock-y += gpio.c
|
||||
|
||||
romstage-y += romstage.c
|
||||
|
||||
ramstage-y += devtree.c
|
||||
ramstage-y += gpio.c
|
||||
ramstage-y += hda_verb.c
|
||||
14
src/mainboard/starlabs/starfighter/variants/rpl/board.fmd
Normal file
14
src/mainboard/starlabs/starfighter/variants/rpl/board.fmd
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
FLASH 0x2000000 {
|
||||
SI_ALL 0x1000000 {
|
||||
SI_DESC 0x1000
|
||||
SI_ME 0x508000
|
||||
}
|
||||
SI_BIOS 0x1000000 {
|
||||
EC@0x0 0x20000
|
||||
RW_MRC_CACHE@0x20000 0x10000
|
||||
SMMSTORE@0x30000 0x40000
|
||||
CONSOLE@0x70000 0x20000
|
||||
FMAP@0x90000 0x1000
|
||||
COREBOOT(CBFS)
|
||||
}
|
||||
}
|
||||
BIN
src/mainboard/starlabs/starfighter/variants/rpl/data.vbt
Normal file
BIN
src/mainboard/starlabs/starfighter/variants/rpl/data.vbt
Normal file
Binary file not shown.
270
src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
Normal file
270
src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
Normal file
|
|
@ -0,0 +1,270 @@
|
|||
chip soc/intel/alderlake
|
||||
# FSP UPDs
|
||||
register "disable_dynamic_tccold_handshake" = "true"
|
||||
register "eist_enable" = "true"
|
||||
register "enable_c1e" = "true"
|
||||
register "enable_c6dram" = "true"
|
||||
register "sagv" = "SaGv_Enabled"
|
||||
|
||||
# Serial I/O
|
||||
register "serial_io_i2c_mode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
||||
}"
|
||||
|
||||
register "common_soc_config" = "{
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
}"
|
||||
|
||||
register "serial_io_uart_mode" = "{
|
||||
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
|
||||
}"
|
||||
|
||||
# Power
|
||||
register "pch_slp_s3_min_assertion_width" = "2" # 50ms
|
||||
register "pch_slp_s4_min_assertion_width" = "3" # 1s
|
||||
register "pch_slp_sus_min_assertion_width" = "3" # 500ms
|
||||
register "pch_slp_a_min_assertion_width" = "3" # 2s
|
||||
|
||||
device domain 0 on
|
||||
device ref igpu on
|
||||
register "ddi_portA_config" = "1"
|
||||
register "ddi_ports_config" = "{
|
||||
[DDI_PORT_A] = DDI_ENABLE_HPD,
|
||||
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
|
||||
}"
|
||||
end
|
||||
device ref pcie4_0 on # SSD x4
|
||||
register "cpu_pcie_rp[CPU_RP(1)]" = "{
|
||||
.clk_src = 4,
|
||||
.clk_req = 4,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
|
||||
}"
|
||||
smbios_slot_desc "SlotTypeM2Socket3"
|
||||
"SlotLengthLong"
|
||||
"M.2/M 2280"
|
||||
"SlotDataBusWidth4X"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)"
|
||||
register "srcclk_pin" = "4"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref tbt_pcie_rp0 on end
|
||||
device ref tbt_pcie_rp1 on end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left Back USB Type-C""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left Front USB Type-C""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
device ref tcss_usb3_port2 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_dma0 on
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
|
||||
use tcss_usb3_port1 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
|
||||
use tcss_usb3_port2 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref gna on end
|
||||
device ref xhci on
|
||||
# Motherboard USB Type C #0
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
|
||||
|
||||
# Motherboard USB Type-C #1
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
|
||||
|
||||
# Motherboard USB Type-A #0
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
|
||||
|
||||
# Removable Webcam
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
|
||||
# I/O Board USB Type-A
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
|
||||
|
||||
# Internal Bluetooth
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left Back USB Type-C""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left Front USB Type-C""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
device ref usb2_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left USB Type-A""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left USB Type-A""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Right USB Type-A""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Right USB Type-A""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Internal Webcam""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Internal Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref i2c0 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""STAR0001""
|
||||
register "generic.desc" = ""Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D11_IRQ)"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 2c on end
|
||||
end
|
||||
end
|
||||
device ref shared_sram on end
|
||||
device ref sata on
|
||||
register "sata_salp_support" = "1"
|
||||
register "sata_ports_enable[1]" = "1"
|
||||
register "sata_ports_dev_slp[1]" = "1"
|
||||
end
|
||||
device ref pcie_rp5 on # WiFi
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device generic 0 on end
|
||||
end
|
||||
register "pch_pcie_rp[PCH_RP(5)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
smbios_slot_desc "SlotTypePciExpressGen3X1"
|
||||
"SlotLengthShort"
|
||||
"M.2/M 2230"
|
||||
"SlotDataBusWidth1X"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
|
||||
register "srcclk_pin" = "2"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device ref pcie_rp9 on # SSD x4
|
||||
register "pch_pcie_rp[PCH_RP(9)]" = "{
|
||||
.clk_src = 1,
|
||||
.clk_req = 1,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
.pcie_rp_detect_timeout_ms = 50,
|
||||
}"
|
||||
smbios_slot_desc "SlotTypeM2Socket3"
|
||||
"SlotLengthLong"
|
||||
"M.2/M 2280"
|
||||
"SlotDataBusWidth4X"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
|
||||
register "srcclk_pin" = "1"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref uart0 on end
|
||||
device ref pch_espi on
|
||||
register "gen1_dec" = "0x00fc0201"
|
||||
register "gen2_dec" = "0x00000381"
|
||||
register "gen3_dec" = "0x00000511"
|
||||
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
|
||||
chip ec/starlabs/merlin
|
||||
# Port pair 4Eh/4Fh
|
||||
device pnp 4e.00 on end # IO Interface
|
||||
device pnp 4e.01 off end # Com 1
|
||||
device pnp 4e.02 off end # Com 2
|
||||
device pnp 4e.04 off end # System Wake-Up
|
||||
device pnp 4e.05 off end # PS/2 Mouse
|
||||
device pnp 4e.06 on # PS/2 Keyboard
|
||||
io 0x60 = 0x0060
|
||||
io 0x62 = 0x0064
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 4e.0a off end # Consumer IR
|
||||
device pnp 4e.0f off end # Shared Memory/Flash Interface
|
||||
device pnp 4e.10 off end # RTC-like Timer
|
||||
device pnp 4e.11 off end # Power Management Channel 1
|
||||
device pnp 4e.12 off end # Power Management Channel 2
|
||||
device pnp 4e.13 off end # Serial Peripheral Interface
|
||||
device pnp 4e.14 off end # Platform EC Interface
|
||||
device pnp 4e.17 off end # Power Management Channel 3
|
||||
device pnp 4e.18 off end # Power Management Channel 4
|
||||
device pnp 4e.19 off end # Power Management Channel 5
|
||||
end
|
||||
end
|
||||
device ref pmc hidden
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port1 as usb2_port
|
||||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port2 as usb2_port
|
||||
use tcss_usb3_port2 as usb3_port
|
||||
device generic 1 alias conn1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref hda on
|
||||
subsystemid 0x10ec 0x1200
|
||||
register "pch_hda_sdi_enable[0]" = "1"
|
||||
register "pch_hda_audio_link_hda_enable" = "1"
|
||||
register "pch_hda_idisp_codec_enable" = "1"
|
||||
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
|
||||
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
|
||||
end
|
||||
device ref smbus on end
|
||||
end
|
||||
end
|
||||
67
src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
Normal file
67
src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <chip.h>
|
||||
#include <cpu/intel/turbo.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <option.h>
|
||||
#include <types.h>
|
||||
#include <variants.h>
|
||||
|
||||
void devtree_update(void)
|
||||
{
|
||||
config_t *cfg = config_of_soc();
|
||||
|
||||
struct soc_intel_common_config *common_config;
|
||||
common_config = chip_get_common_soc_structure();
|
||||
|
||||
struct soc_power_limits_config *soc_conf_6core =
|
||||
&cfg->power_limits_config[RPL_P_282_242_142_15W_CORE];
|
||||
|
||||
struct soc_power_limits_config *soc_conf_14core =
|
||||
&cfg->power_limits_config[RPL_P_682_642_482_45W_CORE];
|
||||
|
||||
struct device *tbt_pci_dev_0 = pcidev_on_root(0x07, 0);
|
||||
struct device *tbt_pci_dev_1 = pcidev_on_root(0x07, 0);
|
||||
struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2);
|
||||
|
||||
/* Update PL1 & PL2 based on CMOS settings */
|
||||
switch (get_power_profile(PP_POWER_SAVER)) {
|
||||
case PP_POWER_SAVER:
|
||||
soc_conf_6core->tdp_pl1_override = 15;
|
||||
soc_conf_14core->tdp_pl1_override = 15;
|
||||
soc_conf_6core->tdp_pl2_override = 15;
|
||||
soc_conf_14core->tdp_pl2_override = 15;
|
||||
common_config->pch_thermal_trip = 30;
|
||||
break;
|
||||
case PP_BALANCED:
|
||||
soc_conf_6core->tdp_pl1_override = 15;
|
||||
soc_conf_14core->tdp_pl1_override = 15;
|
||||
soc_conf_6core->tdp_pl2_override = 20;
|
||||
soc_conf_14core->tdp_pl2_override = 25;
|
||||
common_config->pch_thermal_trip = 25;
|
||||
break;
|
||||
case PP_PERFORMANCE:
|
||||
soc_conf_6core->tdp_pl1_override = 15;
|
||||
soc_conf_14core->tdp_pl1_override = 28;
|
||||
soc_conf_6core->tdp_pl2_override = 25;
|
||||
soc_conf_14core->tdp_pl2_override = 40;
|
||||
common_config->pch_thermal_trip = 20;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable/Disable Bluetooth based on CMOS settings */
|
||||
if (get_uint_option("wireless", 1) == 0)
|
||||
cfg->usb2_ports[9].enable = 0;
|
||||
|
||||
/* Enable/Disable Webcam based on CMOS settings */
|
||||
if (get_uint_option("webcam", 1) == 0)
|
||||
cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0;
|
||||
|
||||
/* Enable/Disable Thunderbolt based on CMOS settings */
|
||||
if (get_uint_option("thunderbolt", 1) == 0) {
|
||||
tbt_pci_dev_0->enabled = 0;
|
||||
tbt_pci_dev_1->enabled = 0;
|
||||
tbt_dma_dev->enabled = 0;
|
||||
}
|
||||
}
|
||||
454
src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
Normal file
454
src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
Normal file
|
|
@ -0,0 +1,454 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <variants.h>
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
const struct pad_config early_gpio_table[] = {
|
||||
/* H10: UART0 RXD Debug Connector */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11: UART0 TXD Debug Connector */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
/* F12: Board ID 0 */
|
||||
PAD_CFG_GPI_LOCK(GPP_F12, NONE, LOCK_CONFIG),
|
||||
/* F13: Board ID 1 */
|
||||
PAD_CFG_GPI_LOCK(GPP_F13, NONE, LOCK_CONFIG),
|
||||
/* F14: Board ID 2 */
|
||||
PAD_CFG_GPI_LOCK(GPP_F14, NONE, LOCK_CONFIG),
|
||||
/* F15: Board ID 3 */
|
||||
PAD_CFG_GPI_LOCK(GPP_F15, NONE, LOCK_CONFIG),
|
||||
|
||||
};
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
const struct pad_config gpio_table[] = {
|
||||
/* GPD0: Battery Low */
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* GPD1: Charger Connected */
|
||||
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* GPD2: LAN Wake */
|
||||
PAD_NC(GPD2, NONE),
|
||||
/* GPD3: Power Button */
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
/* GPD4: Sleep S3 */
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* GPD5: Sleep S4 */
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* GPD6: Sleep A */
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
/* GPD7: Power Adapter Disable */
|
||||
PAD_CFG_GPO(GPD7, 0, PWROK),
|
||||
/* GPD8: Suspend Clock */
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* GPD9: Wireless LAN Sleep */
|
||||
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
/* GPD10: Sleep S5 */
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
/* GPD11: LAN PHY Enable */
|
||||
PAD_NC(GPD11, NONE),
|
||||
|
||||
/* A0: ESPI IO 0 */
|
||||
/* A1: ESPI IO 1 */
|
||||
/* A2: ESPI IO 2 */
|
||||
/* A3: ESPI IO 3 */
|
||||
/* A4: ESPI CS 0 */
|
||||
/* A5: Not Connected */
|
||||
PAD_NC(GPP_A5, NONE),
|
||||
/* A6: Not Connected */
|
||||
PAD_NC(GPP_A6, NONE),
|
||||
/* A7: Embedded Controller SCI */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, PLTRST, LEVEL),
|
||||
/* A8: Not Connected */
|
||||
PAD_NC(GPP_A8, NONE),
|
||||
/* A9: ESPI Clock */
|
||||
/* A10: ESPI Reset */
|
||||
/* A11: Not Connected */
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
/* A12: PCH M.2 SSD PEDET */
|
||||
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
|
||||
/* A13: BlueTooth RF Kill */
|
||||
PAD_CFG_GPO(GPP_A13, 1, DEEP),
|
||||
/* A14: Test Point 45 */
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
/* A15: Test Point 52 */
|
||||
PAD_NC(GPP_A15, NONE),
|
||||
/* A16: USB OverCurrent 3 */
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
/* A17: Not Connected */
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
/* A18: DDI B DP HPD */
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
/* A19: Not Connected */
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
/* A20: Test Point 44 */
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
/* A21: Not Connected */
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
/* A22: Not Connected */
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
/* A23: Not Connected */
|
||||
PAD_NC(GPP_A23, NONE),
|
||||
|
||||
|
||||
/* B0: Core Vendor ID 0 */
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
/* B1: Core Vendor ID 1 */
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
/* B2: BC PROCHOT */
|
||||
PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
|
||||
/* B3: Not Connected */
|
||||
PAD_NC(GPP_B3, NONE),
|
||||
/* B4: Not Connected */
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
/* B5: I2C 2 SDA Touch Panel SDA */
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
/* B6: I2C 2 SCL Touch Panel Clock */
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
/* B7: I2C 3 SDA Test Point 15 */
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
/* B8: I2C 3 SCL Test Point 16 */
|
||||
PAD_NC(GPP_B8, NONE),
|
||||
/* B9: Not Connected */
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
/* B10: Not Connected */
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
/* B11: I2C PMC PD Interrupt */
|
||||
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
|
||||
/* B12: PM SLP S0 */
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* B13: PLT RST */
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* B14: Not Connected */
|
||||
PAD_NC(GPP_B14, NONE),
|
||||
/* B15: Not Connected */
|
||||
PAD_NC(GPP_B15, NONE),
|
||||
/* B16: Not Connected */
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
/* B17: Not Connected */
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
/* B18: Not Connected */
|
||||
PAD_NC(GPP_B18, NONE),
|
||||
/* B19: Not Connected */
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
/* B20: Not Connected */
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
/* B21: Not Connected */
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
/* B22: Not Connected */
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
/* B23: Not Connected */
|
||||
PAD_NC(GPP_B23, NONE),
|
||||
/* B24: Not Connected */
|
||||
PAD_NC(GPP_B24, NONE),
|
||||
/* B25: Not Connected */
|
||||
PAD_NC(GPP_B25, NONE),
|
||||
|
||||
/* C0: SMB Clock */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
/* C1: SMB Data */
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
/* C2: TLS Confidentiality Weak Internal PD 20K
|
||||
Low: Disabled
|
||||
High: Enabled */
|
||||
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
|
||||
/* C3: SML 0 Clock */
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
/* C4: SML 0 Data */
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
/* C5: Boot Strap Weak Internal PD 20K
|
||||
Low: ESPI
|
||||
High: Disabled */
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP),
|
||||
/* C6: SML 1 Clock */
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
/* C7: SML 1 Data */
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
/* C8: Not Connected */
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
/* C9: Not Connected */
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
/* C10: Not Connected */
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
/* C11: Not Connected */
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
/* C12: Not Connected */
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
/* C13: Not Connected */
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
/* C14: Not Connected */
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
/* C15: Not Connected */
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
/* C16: Not Connected */
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
/* C17: Not Connected */
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
/* C18: Not Connected */
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
/* C19: Not Connected */
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
/* C20: Not Connected */
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
/* C21: Not Connected */
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
/* C22: Not Connected */
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
/* C23: Not Connected */
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
|
||||
/* D0: Not used Audio ID 0 */
|
||||
PAD_NC(GPP_D0, NONE),
|
||||
/* D1: Not used Audio ID 1 */
|
||||
PAD_NC(GPP_D1, NONE),
|
||||
/* D2: Not used Audio ID 2 */
|
||||
PAD_NC(GPP_D2, NONE),
|
||||
/* D3: Not Connected */
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
/* D4: Not Connected */
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
/* D5: Clock Request 0 */
|
||||
PAD_NC(GPP_D5, NONE),
|
||||
/* D6: Clock Request 1 PCH M.2 SSD */
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
/* D7: Clock Request 2 Wireless LAN */
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
/* D8: Clock Request 3 LAN */
|
||||
PAD_NC(GPP_D8, NONE),
|
||||
/* D9: PWD_AMP_IN */
|
||||
PAD_NC(GPP_D9, NONE),
|
||||
/* D10: TPM_IRQ */
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
/* D11: TCHPAD_INT_N */
|
||||
PAD_CFG_GPI_APIC_LOW(GPP_D11, NONE, PLTRST),
|
||||
/* D12: ES8336_INT_N */
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
/* D13: Wireless LAN Wake */
|
||||
PAD_CFG_GPO(GPP_D13, 1, PLTRST),
|
||||
/* D14: CPU M.2 SSD Power Enable */
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
/* D15: Not Connected */
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
/* D16: PCH M.2 SSD Power Enable */
|
||||
PAD_CFG_GPO(GPP_D16, 1, PLTRST),
|
||||
/* D17: Not used Fingerprint ID */
|
||||
PAD_NC(GPP_D17, NONE),
|
||||
/* D18: Trackpad reset */
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
/* D19: I2S_MCLK1_OUT */
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
|
||||
/* E0: SATA x PCIe */
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
/* E1: Not Connected */
|
||||
PAD_NC(GPP_E1, NONE),
|
||||
/* E2: Not Connected */
|
||||
PAD_CFG_GPO(GPP_E2, 1, PLTRST),
|
||||
/* E3: WiFi RF Kill */
|
||||
PAD_CFG_GPO(GPP_E3, 1, DEEP),
|
||||
/* E4: Retimer Force Power */
|
||||
PAD_CFG_GPO(GPP_E4, 0, PLTRST),
|
||||
/* E5: Not Connected */
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
/* E6: JTAG ODT No internal PD
|
||||
Low: Disabled
|
||||
High: Enabled */
|
||||
PAD_CFG_GPO(GPP_E6, 0, DEEP),
|
||||
/* E7: Embedded Controller SMI */
|
||||
PAD_CFG_GPI_SMI_LOW(GPP_E7, NONE, DEEP, EDGE_SINGLE),
|
||||
/* E8: DRAM Sleep */
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
/* E9: USB OverCurrent 0 */
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
/* E10: Not Connected */
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
/* E11: Not Connected */
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
/* E12: Not Connected */
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
/* E13: Not connected */
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
/* E14: EDP HPD */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
/* E15: Not Connected */
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
/* E16: Not Connected */
|
||||
PAD_NC(GPP_E16, NONE),
|
||||
/* E17: Not Connected */
|
||||
PAD_CFG_GPO(GPP_E17, 1, PLTRST),
|
||||
/* E18: Thunderbolt LSX TXD */
|
||||
PAD_NC(GPP_E18, NATIVE),
|
||||
/* E19: Thunderbolt LSX RXD */
|
||||
PAD_NC(GPP_E19, NATIVE),
|
||||
/* E20: TBT_LSX1_TXD */
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
/* E21: TBT_LSX1_RXD */
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
/* E22: Not Connected */
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
/* E23: Not Connected */
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
|
||||
/* F0: CNV BRI Data */
|
||||
PAD_NC(GPP_F0, NONE),
|
||||
/* F1: CNV BRI Response */
|
||||
PAD_NC(GPP_F1, NONE),
|
||||
/* F2: CNV RGI Data */
|
||||
PAD_NC(GPP_F2, NONE),
|
||||
/* F3: CNV RGI Response */
|
||||
PAD_NC(GPP_F3, NONE),
|
||||
/* F4: CNV RF Reset */
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
/* F5: Not used */
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
/* F6: Not used */
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
/* F7: GPPC_F7 */
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
/* F8: Not Connected */
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
/* F9: EC Sleep S0 */
|
||||
PAD_CFG_GPO(GPP_F9, 1, PLTRST),
|
||||
/* F10: Weak Internal PD 20K */
|
||||
PAD_CFG_GPO(GPP_F10, 1, PLTRST),
|
||||
/* F11: TPM ID */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI),
|
||||
/* F16: Not Connected */
|
||||
PAD_CFG_GPO(GPP_F16, 1, RSMRST),
|
||||
/* F17: Not used Touch Panel Reset */
|
||||
PAD_NC(GPP_F17, NONE),
|
||||
/* F18: Not used Touch Panel Interrupt */
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
/* F19: Not Connected */
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
/* F20: CPU M.2 SSD Reset */
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST),
|
||||
/* F21: GPPC_F21 */
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
/* F22: Not Connected */
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
/* F23: Not Connected */
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
|
||||
/* H0: PCH M.2 SSD Reset */
|
||||
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
|
||||
/* H1: BFX Strap 2 Bit 3 Weak Internal PD 20K */
|
||||
PAD_CFG_GPO(GPP_H1, 1, PLTRST),
|
||||
/* H2: Wireless LAN Reset */
|
||||
PAD_CFG_GPO(GPP_H2, 1, PLTRST),
|
||||
/* H3: Not Connected */
|
||||
PAD_NC(GPP_H3, NONE),
|
||||
/* H4: I2C 0 SDA Touchpad */
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
/* H5: I2C 0 SDL Touchpad */
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
/* H6: Not Connected */
|
||||
PAD_NC(GPP_H6, NONE),
|
||||
/* H7: Not Connected */
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
/* H8: Not Connected */
|
||||
PAD_NC(GPP_H8, NONE),
|
||||
/* H9: Not Connected */
|
||||
PAD_NC(GPP_H9, NONE),
|
||||
/* H12: Not Connected */
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
/* H13: PCH M.2 SSD Device Sleep */
|
||||
PAD_CFG_GPO(GPP_H13, 0, PLTRST),
|
||||
/* H14: Not Connected */
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
/* H15: DDPB Control Clock */
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
/* H16: Not Connected */
|
||||
PAD_NC(GPP_H16, NONE),
|
||||
/* H17: DDPB Control Data */
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
/* H18: CPI C10 Gate */
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
/* H19: Clock Request 4 CPU M.2 SSD */
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
|
||||
/* H20: Not Connected */
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
/* H21: Not Connected */
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
/* H22: Not Connected */
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
/* H23: Clock Request 5 */
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
|
||||
/* S0: Not Connected */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
/* S1: Not Connected */
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
/* S2: DMIC Clock */
|
||||
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
|
||||
/* S3: DMIC Data */
|
||||
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
|
||||
/* S4: Not Connected */
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
/* S5: Not Connected */
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
/* S6: Not Connected */
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
/* S7: Not Connected */
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
|
||||
/* T0: Not Connected */
|
||||
PAD_NC(GPP_T0, NONE),
|
||||
/* T1: Not Connected */
|
||||
PAD_NC(GPP_T1, NONE),
|
||||
/* T2: Not Connected */
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
/* T3: Not Connected */
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
/* T4: Not Connected */
|
||||
PAD_NC(GPP_T4, NONE),
|
||||
/* T5: Not Connected */
|
||||
PAD_NC(GPP_T5, NONE),
|
||||
/* T6: Not Connected */
|
||||
PAD_NC(GPP_T6, NONE),
|
||||
/* T7: Not Connected */
|
||||
PAD_NC(GPP_T7, NONE),
|
||||
/* T8: Not Connected */
|
||||
PAD_NC(GPP_T8, NONE),
|
||||
/* T9: Not Connected */
|
||||
PAD_NC(GPP_T9, NONE),
|
||||
/* T10: Not Connected */
|
||||
PAD_NC(GPP_T10, NONE),
|
||||
/* T11: Not Connected */
|
||||
PAD_NC(GPP_T11, NONE),
|
||||
/* T12: Not Connected */
|
||||
PAD_NC(GPP_T12, NONE),
|
||||
/* T13: Not Connected */
|
||||
PAD_NC(GPP_T13, NONE),
|
||||
/* T14: Not Connected */
|
||||
PAD_NC(GPP_T14, NONE),
|
||||
/* T15: Not Connected */
|
||||
PAD_NC(GPP_T15, NONE),
|
||||
|
||||
/* R0: HDA BCLK */
|
||||
PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),
|
||||
/* R1: HDA SYNC */
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
/* R2: HDA SDO */
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
/* R3: HDA SDI */
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
/* R4: HDA Reset */
|
||||
PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),
|
||||
/* R5: MiPi Cam Reset */
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
/* R6: Not Connected */
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
/* R7: Not Connected */
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
184
src/mainboard/starlabs/starfighter/variants/rpl/hda_verb.c
Normal file
184
src/mainboard/starlabs/starfighter/variants/rpl/hda_verb.c
Normal file
|
|
@ -0,0 +1,184 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */
|
||||
0x10ec1200, /* Subsystem ID */
|
||||
32, /* Number of jacks (NID entries) */
|
||||
|
||||
/* Reset Codec First */
|
||||
AZALIA_RESET(0x1),
|
||||
|
||||
/* HDA Codec Subsystem ID: 0x10EC1200 */
|
||||
AZALIA_SUBVENDOR(0, 0x10ec1200),
|
||||
|
||||
AZALIA_PIN_CFG(0, 0x01, 0x00000000),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x04a19040),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40689a6d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x04214020),
|
||||
|
||||
/* Reset and Set LDO3 output to 1.2V */
|
||||
0x0205001a,
|
||||
0x0204c003,
|
||||
0x02050019,
|
||||
0x02040f52,
|
||||
/* ALC256 Relay 1 */
|
||||
0x0205001b,
|
||||
0x0204064b,
|
||||
0x02050045,
|
||||
0x0204b089,
|
||||
/* ALC256 Relay 2 */
|
||||
0x02050046,
|
||||
0x02040004,
|
||||
0x02050040,
|
||||
0x02048800,
|
||||
|
||||
/*
|
||||
* Equalizer:
|
||||
*
|
||||
* AGC
|
||||
* Threshold: - 6.00 dB
|
||||
* Front Boost: + 6.00 dB
|
||||
* Post Boost: + 6.00 dB
|
||||
*
|
||||
* Low Pass Filter
|
||||
* Boost Gain: Enabled
|
||||
* BW: 200Hz
|
||||
* Gain: + 4.00 dB
|
||||
*
|
||||
* Band Pass Filter 1
|
||||
* Fc: 240Hz
|
||||
* BW: 400Hz
|
||||
* Gain: - 4.00 dB
|
||||
*
|
||||
* Band Pass Filter 2
|
||||
* Fc: 16000Hz
|
||||
* BW: 1000Hz
|
||||
* Gain: + 12.00 dB
|
||||
*
|
||||
* High Pass Filter
|
||||
* Boost Gain: Enabled
|
||||
* BW: 200Hz
|
||||
* Gain: - 4.00 dB
|
||||
*
|
||||
* Class D Amp
|
||||
* Power: 2.5W
|
||||
* Resistance: 4ohms
|
||||
*
|
||||
* EQ Output
|
||||
* Left: + 0.00 dB
|
||||
* Right: + 0.00 dB
|
||||
*
|
||||
* VARQ
|
||||
* Q: 0.707
|
||||
*/
|
||||
|
||||
0x05350000,
|
||||
0x053404DA,
|
||||
0x0535001d,
|
||||
0x05340800,
|
||||
|
||||
0x0535001e,
|
||||
0x05340800,
|
||||
0x05350003,
|
||||
0x05341F7A,
|
||||
|
||||
0x05350004,
|
||||
0x0534FA18,
|
||||
0x0535000F,
|
||||
0x0534C295,
|
||||
|
||||
0x05350010,
|
||||
0x05341D73,
|
||||
0x05350011,
|
||||
0x0534FA18,
|
||||
|
||||
0x05350012,
|
||||
0x05341E08,
|
||||
0x05350013,
|
||||
0x05341C10,
|
||||
|
||||
0x05350014,
|
||||
0x05342FB2,
|
||||
0x0535001B,
|
||||
0x05341F2C,
|
||||
|
||||
0x0535001C,
|
||||
0x0534095C,
|
||||
0x05450000,
|
||||
0x05440000,
|
||||
|
||||
0x0545001d,
|
||||
0x05440800,
|
||||
0x0545001e,
|
||||
0x05440800,
|
||||
|
||||
0x05450003,
|
||||
0x05441F7A,
|
||||
0x05450004,
|
||||
0x0544FA18,
|
||||
|
||||
0x0545000F,
|
||||
0x0544C295,
|
||||
0x05450010,
|
||||
0x05441D73,
|
||||
|
||||
0x05450011,
|
||||
0x0544FA18,
|
||||
0x05450012,
|
||||
0x05441E08,
|
||||
|
||||
0x05450013,
|
||||
0x05441C10,
|
||||
0x05450014,
|
||||
0x05442FB2,
|
||||
|
||||
0x0545001B,
|
||||
0x05441F2C,
|
||||
0x0545001C,
|
||||
0x0544095C,
|
||||
|
||||
0x05350000,
|
||||
0x0534C4DA,
|
||||
0x02050038,
|
||||
0x02044901,
|
||||
|
||||
0x02050013,
|
||||
0x0204422F,
|
||||
0x02050016,
|
||||
0x02044E50,
|
||||
|
||||
0x02050012,
|
||||
0x0204EBC4,
|
||||
0x02050020,
|
||||
0x020451FF,
|
||||
|
||||
0x80862815, /* Codec Vendor / Device ID: Intel */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of 4 dword sets */
|
||||
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18561010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18561010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18561010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18561010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18561010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18561010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
11
src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
Normal file
11
src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <option.h>
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
|
||||
{
|
||||
if (get_uint_option("thunderbolt", 1) == 0)
|
||||
supd->UsbTcPortEn = 0;
|
||||
}
|
||||
144
src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
Normal file
144
src/mainboard/starlabs/starfighter/variants/rpl/romstage.c
Normal file
|
|
@ -0,0 +1,144 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <option.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <types.h>
|
||||
|
||||
#include <console/console.h>
|
||||
#include <gpio.h>
|
||||
|
||||
static uint8_t get_memory_config_straps(void)
|
||||
{
|
||||
/*
|
||||
* The hardware supports a number of different memory configurations
|
||||
* which are selected using four ID bits ID3 (GPP_F15), ID2 (GPP_F14),
|
||||
* ID1 (GPP_F13) and ID0 (GPP_F12).
|
||||
*
|
||||
*
|
||||
* +------+-----+-----+-----+-----+
|
||||
* | | ID3 | ID2 | ID1 | ID0 |
|
||||
* +------+-----+-----+-----+-----+
|
||||
* | 16GB | 0 | 0 | 0 | 0 |
|
||||
* +------+-----+-----+-----+-----+
|
||||
* | 32GB | 1 | 0 | 0 | 0 |
|
||||
* +------+-----+-----+-----+-----+
|
||||
* | 64GB | 1 | 1 | 0 | 1 |
|
||||
* +------+-----+-----+-----+-----+
|
||||
*
|
||||
* We return the value of these bits so that the index into the SPD
|
||||
* table can be .spd[] values can be configured correctly in the
|
||||
* memory configuration structure.
|
||||
*/
|
||||
|
||||
gpio_t spd_id[] = {
|
||||
GPP_F15,
|
||||
GPP_F14,
|
||||
GPP_F13,
|
||||
GPP_F12,
|
||||
};
|
||||
|
||||
return (uint8_t)gpio_base2_value(spd_id, ARRAY_SIZE(spd_id));
|
||||
}
|
||||
|
||||
static uint8_t strap_to_cbfs_index(uint8_t strap)
|
||||
{
|
||||
switch (strap) {
|
||||
case 0: // 32GB
|
||||
return 1;
|
||||
case 8: // 64GB
|
||||
return 2;
|
||||
default:// 16GB
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
const struct mb_cfg mem_config = {
|
||||
.type = MEM_TYPE_LP5X,
|
||||
|
||||
.lpx_dq_map = {
|
||||
.ddr0 = {
|
||||
.dq0 = { 5, 0, 4, 1, 2, 6, 7, 3 },
|
||||
.dq1 = { 11, 15, 13, 12, 10, 14, 8, 9 },
|
||||
},
|
||||
.ddr1 = {
|
||||
.dq0 = { 9, 10, 11, 8, 13, 14, 12, 15 },
|
||||
.dq1 = { 0, 2, 1, 3, 7, 5, 6, 4 },
|
||||
},
|
||||
.ddr2 = {
|
||||
.dq0 = { 3, 7, 2, 6, 4, 1, 5, 0 },
|
||||
.dq1 = { 12, 14, 15, 13, 11, 10, 8, 9 },
|
||||
},
|
||||
.ddr3 = {
|
||||
.dq0 = { 15, 14, 12, 13, 10, 9, 11, 8 },
|
||||
.dq1 = { 7, 6, 4, 5, 0, 3, 1, 2 },
|
||||
},
|
||||
.ddr4 = {
|
||||
.dq0 = { 15, 14, 12, 13, 10, 9, 8, 11 },
|
||||
.dq1 = { 1, 3, 0, 2, 5, 6, 7, 4 },
|
||||
},
|
||||
.ddr5 = {
|
||||
.dq0 = { 9, 10, 11, 8, 12, 15, 13, 14 },
|
||||
.dq1 = { 3, 7, 2, 6, 0, 4, 5, 1 },
|
||||
},
|
||||
.ddr6 = {
|
||||
.dq0 = { 11, 8, 10, 9, 12, 14, 13, 15 },
|
||||
.dq1 = { 0, 7, 1, 2, 6, 4, 3, 5 },
|
||||
},
|
||||
.ddr7 = {
|
||||
.dq0 = { 1, 2, 3, 0, 7, 5, 6, 4 },
|
||||
.dq1 = { 15, 14, 11, 13, 8, 9, 12, 10 }
|
||||
},
|
||||
},
|
||||
|
||||
/* DQS CPU<>DRAM map */
|
||||
.lpx_dqs_map = {
|
||||
.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
},
|
||||
|
||||
.ect = true,
|
||||
|
||||
.LpDdrDqDqsReTraining = 1,
|
||||
|
||||
.UserBd = BOARD_TYPE_MOBILE,
|
||||
.lp5x_config = {
|
||||
.ccc_config = 0xff,
|
||||
}
|
||||
};
|
||||
|
||||
const bool half_populated = false;
|
||||
|
||||
const struct mem_spd lpddr5_spd_info = {
|
||||
.topo = MEM_TOPO_MEMORY_DOWN,
|
||||
.cbfs_index = strap_to_cbfs_index(get_memory_config_straps()),
|
||||
};
|
||||
|
||||
memcfg_init(mupd, &mem_config, &lpddr5_spd_info, half_populated);
|
||||
|
||||
const uint8_t vtd = get_uint_option("vtd", 1);
|
||||
mupd->FspmConfig.VtdDisable = !vtd;
|
||||
|
||||
/* Enable/Disable Wireless (RP05) based on CMOS settings */
|
||||
if (get_uint_option("wireless", 1) == 0)
|
||||
mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 4);
|
||||
|
||||
/* Enable/Disable Thunderbolt based on CMOS settings */
|
||||
if (get_uint_option("thunderbolt", 1) == 0) {
|
||||
mupd->FspmConfig.VtdItbtEnable = 0;
|
||||
mupd->FspmConfig.VtdBaseAddress[3] = 0;
|
||||
mupd->FspmConfig.TcssDma0En = 0;
|
||||
mupd->FspmConfig.TcssItbtPcie0En = 0;
|
||||
mupd->FspmConfig.TcssXhciEn = 0;
|
||||
}
|
||||
|
||||
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
|
||||
};
|
||||
8
src/mainboard/starlabs/starfighter/vboot.c
Normal file
8
src/mainboard/starlabs/starfighter/vboot.c
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <bootmode.h>
|
||||
|
||||
int get_recovery_mode_switch(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue