erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/xeon_sp: Use MemoryMapDataHob to add high RAM resources

Browse source 
On GNR, there are CXL Type-3 memory windows covered under TOHM. The
current 4GB to TOHM DRAM reporting doesn't work on GNR.

Use MemoryMapDataHob to add high RAM resources as a generic
mechanism for GNR and previous generation SoCs.

TEST=Build and boot on intel/archercity CRB
TEST=Build and boot on intel/beechnutcity CRB
(with topic:"Xeon6-Basic-Boot")

Change-Id: Ie5fbc5735704d95c7ad50740ff0e35737afdbd80
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84304
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shuo Liu 2024-05-16 06:13:10 +08:00 • committed by Felix Held
commit 1bebdc0d72
1 changed files with 17 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

36
src/soc/intel/xeon_sp/uncore.c
View file

@ -284,21 +284,25 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
mc_values[TOLM_REG]);
LOG_RESOURCE("mmio_tolm", dev, res);
if (CONFIG(SOC_INTEL_HAS_CXL)) {
/* 4GiB -> CXL Memory */
uint32_t gi_mem_size;
gi_mem_size = get_generic_initiator_mem_size(); /* unit: 64MB */
/*
* Memory layout when there is CXL HDM (Host-managed Device Memory):
* -------------- <- TOHM
* CXL memory regions (pds global variable records the base/size of them)
* Processor attached high memory
* -------------- <- 0x100000000 (4GB)
*/
res = upper_ram_end(dev, index++,
mc_values[TOHM_REG] - ((uint64_t)gi_mem_size << 26) + 1);
LOG_RESOURCE("high_ram", dev, res);
/* Add high RAM */
const struct SystemMemoryMapHob *mm = get_system_memory_map();
for (int i = 0; i < mm->numberEntries; i++) {
const struct SystemMemoryMapElement *e = &mm->Element[i];
uint64_t addr = ((uint64_t)e->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS);
uint64_t size = ((uint64_t)e->ElementSize << MEM_ADDR_64MB_SHIFT_BITS);
if (addr < 4ULL * GiB)
continue;
if (!is_memtype_processor_attached(e->Type))
continue;
if (is_memtype_reserved(e->Type))
continue;
res = ram_range(dev, index++, addr, size);
LOG_RESOURCE("high_ram", dev, res);
}
if (CONFIG(SOC_INTEL_HAS_CXL)) {
/* CXL Memory */
uint8_t i;
for (i = 0; i < pds.num_pds; i++) {
@ -320,10 +324,6 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
else
LOG_RESOURCE("CXL_memory", dev, res);
}
} else {
/* 4GiB -> TOHM */
res = upper_ram_end(dev, index++, mc_values[TOHM_REG] + 1);
LOG_RESOURCE("high_ram", dev, res);
}
/* add MMIO CFG resource */