soc/intel/pantherlake: Add FSP-S programming
FSP-S UPDs are programmed according to the configuration (Kconfig and
device tree) in ramstage.
BUG=348678529
TEST=Hardware is programmed as desired and Intel Panther Lake
reference board boots to UI.
Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84552
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Jeremy Compostella
Subrata Banik
parent
d6a4b27e3e
commit
5052271f52
1 changed files with 743 additions and 1 deletions
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@ -1,16 +1,745 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootmode.h>
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#include <cpu/intel/microcode.h>
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#include <fsp/api.h>
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#include <fsp/fsp_debug_event.h>
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#include <fsp/fsp_gop_blt.h>
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#include <fsp/ppi/mp_service_ppi.h>
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#include <intelblocks/irq.h>
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#include <intelblocks/mp_init.h>
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#include <intelblocks/systemagent.h>
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#include <intelblocks/xdci.h>
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#include <intelpch/lockdown.h>
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#include <option.h>
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#include <soc/cpu.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/pcie.h>
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#include <soc/ramstage.h>
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#define MAX_ONBOARD_PCIE_DEVICES 256
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/* THC assignment definition */
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enum {
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THC_NONE,
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THC_0,
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THC_1
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};
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/* LPSS UART Power Gating mode */
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enum {
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LPSS_UART_PG_DISABLED,
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LPSS_UART_PG_ENABLED,
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LPSS_UART_PG_AUTO
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};
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static const pci_devfn_t i2c_dev[] = {
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PCI_DEVFN_I2C0,
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PCI_DEVFN_I2C1,
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PCI_DEVFN_I2C2,
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PCI_DEVFN_I2C3,
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PCI_DEVFN_I2C4,
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PCI_DEVFN_I2C5,
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};
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static const pci_devfn_t uart_dev[] = {
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PCI_DEVFN_UART0,
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PCI_DEVFN_UART1,
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PCI_DEVFN_UART2
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};
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static const pci_devfn_t gspi_dev[] = {
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PCI_DEVFN_GSPI0,
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PCI_DEVFN_GSPI1,
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PCI_DEVFN_GSPI2
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};
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/*
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* Chip config parameter PcieRpL1Substates uses (UPD value + 1)
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* because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
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* In order to ensure that mainboard setting does not disable L1 substates
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* incorrectly, chip config parameter values are offset by 1 with 0 meaning
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* use FSP UPD default. get_l1_substate_control() ensures that the right UPD
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* value is set in fsp_params.
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* 0: Use FSP UPD default
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* 1: Disable L1 substates
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* 2: Use L1.1
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* 3: Use L1.2 (FSP UPD default)
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*/
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static int get_l1_substate_control(enum L1_substates_control ctl)
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{
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if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
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ctl = L1_SS_DISABLED;
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else if (ctl > L1_SS_L1_2 || ctl == L1_SS_FSP_DEFAULT)
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ctl = L1_SS_L1_2;
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return ctl - 1;
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}
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/*
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* Chip config parameter pcie_rp_aspm uses (UPD value + 1) because
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* a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure
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* that the mainboard setting does not disable ASPM incorrectly, chip
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* config parameter values are offset by 1 with 0 meaning use FSP UPD default.
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* get_aspm_control() ensures that the right UPD value is set in fsp_params.
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* 0: Use FSP UPD default
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* 1: Disable ASPM
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* 2: L0s only
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* 3: L1 only
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* 4: L0s and L1
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* 5: Auto configuration
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*/
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static unsigned int get_aspm_control(enum ASPM_control ctl)
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{
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if (ctl > ASPM_AUTO || ctl == ASPM_DEFAULT)
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ctl = ASPM_AUTO;
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return ctl - 1;
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}
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__weak void mainboard_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
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{
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/* Override settings per board. */
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}
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static const struct slot_irq_constraints irq_constraints[] = {
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{
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.slot = PCI_DEV_SLOT_IGD,
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.fns = {
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/* INTERRUPT_PIN is RO/0x01 */
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FIXED_INT_ANY_PIRQ(PCI_DEVFN_IGD, PCI_INT_A),
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},
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},
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{
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.slot = PCI_DEV_SLOT_DPTF,
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.fns = {
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/* Dynamic Tuning Technology (DTT) device IRQ is not
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programmable and is INT_A/PIRQ_A (IRQ 16) */
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FIXED_INT_PIRQ(PCI_DEVFN_DPTF, PCI_INT_A, PIRQ_A),
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},
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},
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{
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.slot = PCI_DEV_SLOT_IPU,
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.fns = {
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/* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW,
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but S0ix fails when not set to 16 (b/193434192) */
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FIXED_INT_PIRQ(PCI_DEVFN_IPU, PCI_INT_A, PIRQ_A),
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},
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},
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{
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.slot = PCI_DEV_SLOT_PCIE_2,
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.fns = {
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FIXED_INT_PIRQ(PCI_DEVFN_PCIE9, PCI_INT_A, PIRQ_A),
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FIXED_INT_PIRQ(PCI_DEVFN_PCIE10, PCI_INT_B, PIRQ_B),
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#if CONFIG(SOC_INTEL_PANTHERLAKE_H)
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FIXED_INT_PIRQ(PCI_DEVFN_PCIE11, PCI_INT_C, PIRQ_C),
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FIXED_INT_PIRQ(PCI_DEVFN_PCIE12, PCI_INT_D, PIRQ_D),
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#endif
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},
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},
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{
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.slot = PCI_DEV_SLOT_TBT,
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.fns = {
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ANY_PIRQ(PCI_DEVFN_TBT0),
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ANY_PIRQ(PCI_DEVFN_TBT1),
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ANY_PIRQ(PCI_DEVFN_TBT2),
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ANY_PIRQ(PCI_DEVFN_TBT3),
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},
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},
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{
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.slot = PCI_DEV_SLOT_NPU,
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.fns = {
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/* INTERRUPT_PIN is RO/0x01 */
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FIXED_INT_ANY_PIRQ(PCI_DEVFN_NPU, PCI_INT_A),
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},
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},
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{
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.slot = PCI_DEV_SLOT_TCSS,
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.fns = {
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ANY_PIRQ(PCI_DEVFN_TCSS_XHCI),
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},
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},
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{
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.slot = PCI_DEV_SLOT_THC,
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.fns = {
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ANY_PIRQ(PCI_DEVFN_THC0),
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ANY_PIRQ(PCI_DEVFN_THC1),
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},
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},
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{
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.slot = PCI_DEV_SLOT_ISH,
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.fns = {
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DIRECT_IRQ(PCI_DEVFN_ISH),
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},
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},
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{
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.slot = PCI_DEV_SLOT_XHCI,
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.fns = {
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ANY_PIRQ(PCI_DEVFN_XHCI),
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DIRECT_IRQ(PCI_DEVFN_USBOTG),
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ANY_PIRQ(PCI_DEVFN_CNVI_WIFI),
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},
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},
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{
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.slot = PCI_DEV_SLOT_SIO0,
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.fns = {
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DIRECT_IRQ(PCI_DEVFN_I2C0),
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DIRECT_IRQ(PCI_DEVFN_I2C1),
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DIRECT_IRQ(PCI_DEVFN_I2C2),
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DIRECT_IRQ(PCI_DEVFN_I2C3),
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},
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},
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{
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.slot = PCI_DEV_SLOT_CSE,
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.fns = {
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ANY_PIRQ(PCI_DEVFN_CSE),
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ANY_PIRQ(PCI_DEVFN_CSE_2),
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ANY_PIRQ(PCI_DEVFN_CSE_IDER),
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ANY_PIRQ(PCI_DEVFN_CSE_KT),
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ANY_PIRQ(PCI_DEVFN_CSE_3),
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ANY_PIRQ(PCI_DEVFN_CSE_4),
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},
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},
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{
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.slot = PCI_DEV_SLOT_SIO1,
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.fns = {
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DIRECT_IRQ(PCI_DEVFN_I2C4),
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DIRECT_IRQ(PCI_DEVFN_I2C5),
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DIRECT_IRQ(PCI_DEVFN_UART2),
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},
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},
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{
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.slot = PCI_DEV_SLOT_PCIE_1,
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.fns = {
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FIXED_INT_PIRQ(PCI_DEVFN_PCIE1, PCI_INT_A, PIRQ_A),
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FIXED_INT_PIRQ(PCI_DEVFN_PCIE2, PCI_INT_B, PIRQ_B),
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FIXED_INT_PIRQ(PCI_DEVFN_PCIE3, PCI_INT_C, PIRQ_C),
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FIXED_INT_PIRQ(PCI_DEVFN_PCIE4, PCI_INT_D, PIRQ_D),
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FIXED_INT_PIRQ(PCI_DEVFN_PCIE5, PCI_INT_A, PIRQ_A),
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FIXED_INT_PIRQ(PCI_DEVFN_PCIE6, PCI_INT_B, PIRQ_B),
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FIXED_INT_PIRQ(PCI_DEVFN_PCIE7, PCI_INT_C, PIRQ_C),
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FIXED_INT_PIRQ(PCI_DEVFN_PCIE8, PCI_INT_D, PIRQ_D),
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},
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},
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{
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.slot = PCI_DEV_SLOT_SIO2,
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.fns = {
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/* UART0 shares an interrupt line with TSN0, so must use
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a PIRQ */
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FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART0, PCI_INT_A),
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/* UART1 shares an interrupt line with TSN1, so must use
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a PIRQ */
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FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART1, PCI_INT_B),
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DIRECT_IRQ(PCI_DEVFN_GSPI0),
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DIRECT_IRQ(PCI_DEVFN_GSPI1),
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},
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},
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{
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.slot = PCI_DEV_SLOT_ESPI,
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.fns = {
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ANY_PIRQ(PCI_DEVFN_HDA),
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ANY_PIRQ(PCI_DEVFN_SMBUS),
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ANY_PIRQ(PCI_DEVFN_GBE),
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/* INTERRUPT_PIN is RO/0x01 */
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FIXED_INT_ANY_PIRQ(PCI_DEVFN_NPK, PCI_INT_A),
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},
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},
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};
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static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_pantherlake_config *config)
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{
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size_t i;
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for (i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
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s_cfg->SerialIoI2cMode[i] =
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is_devfn_enabled(i2c_dev[i]) ? config->serial_io_i2c_mode[i] : 0;
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for (i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
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s_cfg->SerialIoLpssSpiCsMode[i] = config->serial_io_gspi_cs_mode[i];
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s_cfg->SerialIoLpssSpiCsState[i] = config->serial_io_gspi_cs_state[i];
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s_cfg->SerialIoLpssSpiMode[i] =
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is_devfn_enabled(gspi_dev[i]) ? config->serial_io_gspi_mode[i] : 0;
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}
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for (i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) {
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s_cfg->SerialIoUartMode[i] = is_devfn_enabled(uart_dev[i]) ?
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config->serial_io_uart_mode[i] : 0;
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s_cfg->SerialIoUartPowerGating[i] = is_devfn_enabled(uart_dev[i]) ?
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LPSS_UART_PG_ENABLED : LPSS_UART_PG_AUTO;
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}
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}
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static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_pantherlake_config *config)
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{
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if (!CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
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return;
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s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
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}
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static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_pantherlake_config *config)
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{
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const struct microcode *microcode;
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size_t length;
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if (!CONFIG(USE_FSP_FEATURE_PROGRAM_ON_APS))
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return;
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/* Locate microcode and pass to FSP-S for 2nd microcode loading */
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microcode = intel_microcode_find();
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if (!microcode)
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return;
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length = get_microcode_size(microcode);
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if (!length)
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return;
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/* Update CPU Microcode patch base address/size */
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s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode;
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s_cfg->MicrocodeRegionSize = (uint32_t)length;
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}
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static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_pantherlake_config *config)
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{
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/* Load VBT before devicetree-specific config. */
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s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get();
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/* Check if IGD is present and fill Graphics init param accordingly */
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s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(PCI_DEVFN_IGD);
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s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
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s_cfg->PavpEnable = CONFIG(PAVP);
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}
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static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_pantherlake_config *config)
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{
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s_cfg->TcssAuxOri = config->tcss_aux_ori;
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/* Explicitly clear this field to avoid using defaults */
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memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg));
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/* D3Cold for TCSS */
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s_cfg->D3ColdEnable = !config->tcss_d3_cold_disable;
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s_cfg->UsbTcPortEn = 0;
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for (size_t i = 0; i < MAX_TYPE_C_PORTS; i++)
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if (config->tcss_ports[i].enable)
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s_cfg->UsbTcPortEn |= BIT(i);
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}
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static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_pantherlake_config *config)
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{
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/* Chipset Lockdown */
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const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
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s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp;
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s_cfg->PchLockDownBiosInterface = lockdown_by_fsp;
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s_cfg->PchUnlockGpioPads = !lockdown_by_fsp;
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s_cfg->RtcMemoryLock = lockdown_by_fsp;
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s_cfg->SkipPamLock = !lockdown_by_fsp;
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/* coreboot will send EOP before loading payload */
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s_cfg->EndOfPostMessage = 0; /* EOP disable */
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s_cfg->CpuCrashLogEnable = CONFIG(SOC_INTEL_CRASHLOG);
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}
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static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_pantherlake_config *config)
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{
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size_t i;
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for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) {
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s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable;
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s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
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s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
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s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
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s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
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if (config->usb2_ports[i].enable)
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s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
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else
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s_cfg->Usb2OverCurrentPin[i] = OC_SKIP;
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s_cfg->PortResetMessageEnable[i] = config->usb2_ports[i].type_c;
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}
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for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) {
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s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable;
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if (config->usb3_ports[i].enable)
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s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
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else
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s_cfg->Usb3OverCurrentPin[i] = OC_SKIP;
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if (config->usb3_ports[i].tx_de_emp) {
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s_cfg->Usb3HsioTxDeEmphEnable[i] = 1;
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s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
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}
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if (config->usb3_ports[i].tx_downscale_amp) {
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s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1;
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s_cfg->Usb3HsioTxDownscaleAmp[i] =
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config->usb3_ports[i].tx_downscale_amp;
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}
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}
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for (i = 0; i < MAX_TYPE_C_PORTS; i++)
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if (config->tcss_ports[i].enable)
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s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
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}
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static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_pantherlake_config *config)
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{
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s_cfg->XdciEnable = xdci_can_enable(PCI_DEVFN_USBOTG);
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}
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static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_pantherlake_config *config)
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{
|
||||
s_cfg->Device4Enable = is_devfn_enabled(PCI_DEVFN_DPTF);
|
||||
}
|
||||
|
||||
static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count)
|
||||
{
|
||||
const struct pci_irq_entry *entry = get_cached_pci_irqs();
|
||||
SI_PCH_DEVICE_INTERRUPT_CONFIG *config;
|
||||
size_t pch_total = 0, cfg_count = 0;
|
||||
|
||||
if (!entry)
|
||||
return NULL;
|
||||
|
||||
/* Count PCH devices */
|
||||
while (entry) {
|
||||
if (is_pch_slot(entry->devfn))
|
||||
pch_total++;
|
||||
entry = entry->next;
|
||||
}
|
||||
|
||||
/* Convert PCH device entries to FSP format */
|
||||
config = calloc(pch_total, sizeof(*config));
|
||||
entry = get_cached_pci_irqs();
|
||||
while (entry) {
|
||||
if (!is_pch_slot(entry->devfn)) {
|
||||
entry = entry->next;
|
||||
continue;
|
||||
}
|
||||
|
||||
config[cfg_count].Device = PCI_SLOT(entry->devfn);
|
||||
config[cfg_count].Function = PCI_FUNC(entry->devfn);
|
||||
config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin;
|
||||
config[cfg_count].Irq = entry->irq;
|
||||
cfg_count++;
|
||||
|
||||
entry = entry->next;
|
||||
}
|
||||
|
||||
*out_count = cfg_count;
|
||||
|
||||
return config;
|
||||
}
|
||||
|
||||
static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints)))
|
||||
die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n");
|
||||
|
||||
size_t pch_count = 0;
|
||||
const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count);
|
||||
|
||||
s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs);
|
||||
s_cfg->NumOfDevIntConfig = pch_count;
|
||||
printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
|
||||
}
|
||||
|
||||
static void evaluate_ssid(const struct device *dev, uint16_t *svid, uint16_t *ssid)
|
||||
{
|
||||
if (!(dev && svid && ssid))
|
||||
return;
|
||||
|
||||
*svid = CONFIG_SUBSYSTEM_VENDOR_ID ? : (dev->subsystem_vendor ? : 0x8086);
|
||||
*ssid = CONFIG_SUBSYSTEM_DEVICE_ID ? : (dev->subsystem_device ? : 0xfffe);
|
||||
}
|
||||
|
||||
/*
|
||||
* Programming SSID before FSP-S is important because SSID registers of a few PCIE
|
||||
* devices (e.g. IPU, Crashlog, XHCI, TCSS_XHCI etc.) are locked after FSP-S hence
|
||||
* provide a custom SSID (same as DID by default) value via UPD.
|
||||
*/
|
||||
static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
struct svid_ssid_init_entry {
|
||||
union {
|
||||
struct {
|
||||
uint64_t reg:12;
|
||||
uint64_t function:3;
|
||||
uint64_t device:5;
|
||||
uint64_t bus:8;
|
||||
uint64_t ignore1:4;
|
||||
uint64_t segment:16;
|
||||
uint64_t ignore2:16;
|
||||
};
|
||||
uint64_t data;
|
||||
};
|
||||
struct {
|
||||
uint16_t svid;
|
||||
uint16_t ssid;
|
||||
};
|
||||
uint32_t ignore3;
|
||||
};
|
||||
|
||||
static struct svid_ssid_init_entry ssid_table[MAX_ONBOARD_PCIE_DEVICES];
|
||||
const struct device *dev;
|
||||
size_t i = 0;
|
||||
|
||||
for (dev = all_devices; dev; dev = dev->next) {
|
||||
if (!(is_dev_enabled(dev) && dev->path.type == DEVICE_PATH_PCI &&
|
||||
dev->upstream->secondary == 0))
|
||||
continue;
|
||||
|
||||
if (dev->path.pci.devfn == PCI_DEVFN_ROOT) {
|
||||
evaluate_ssid(dev, &s_cfg->SiCustomizedSvid, &s_cfg->SiCustomizedSsid);
|
||||
} else {
|
||||
ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID;
|
||||
ssid_table[i].device = PCI_SLOT(dev->path.pci.devfn);
|
||||
ssid_table[i].function = PCI_FUNC(dev->path.pci.devfn);
|
||||
evaluate_ssid(dev, &ssid_table[i].svid, &ssid_table[i].ssid);
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
s_cfg->SiSsidTablePtr = (uintptr_t)ssid_table;
|
||||
s_cfg->SiNumberOfSsidTableEntry = i;
|
||||
|
||||
/* Ensure FSP will program the registers */
|
||||
s_cfg->SiSkipSsidProgramming = 0;
|
||||
}
|
||||
|
||||
static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
s_cfg->PchLanEnable = is_devfn_enabled(PCI_DEVFN_GBE);
|
||||
}
|
||||
|
||||
static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
s_cfg->CnviMode = is_devfn_enabled(PCI_DEVFN_CNVI_WIFI);
|
||||
s_cfg->CnviWifiCore = config->cnvi_wifi_core;
|
||||
s_cfg->CnviBtCore = config->cnvi_bt_core;
|
||||
s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload;
|
||||
|
||||
if (!s_cfg->CnviMode && s_cfg->CnviWifiCore) {
|
||||
printk(BIOS_ERR, "CNVi WiFi is enabled without CNVi being enabled\n");
|
||||
s_cfg->CnviWifiCore = 0;
|
||||
}
|
||||
if (!s_cfg->CnviBtCore && s_cfg->CnviBtAudioOffload) {
|
||||
printk(BIOS_ERR, "BT offload is enabled without CNVi BT being enabled\n");
|
||||
s_cfg->CnviBtAudioOffload = 0;
|
||||
}
|
||||
if (!s_cfg->CnviMode && s_cfg->CnviBtCore) {
|
||||
printk(BIOS_ERR, "CNVi BT is enabled without CNVi being enabled\n");
|
||||
s_cfg->CnviBtCore = 0;
|
||||
s_cfg->CnviBtAudioOffload = 0;
|
||||
}
|
||||
|
||||
s_cfg->CnviBtInterface = is_devfn_enabled(PCI_DEVFN_CNVI_BT) ? 2 : 1;
|
||||
}
|
||||
|
||||
static void fill_fsps_pmcpd_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
s_cfg->PmcPdEnable = 1;
|
||||
}
|
||||
|
||||
static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
s_cfg->ThcAssignment[0] = is_devfn_enabled(PCI_DEVFN_THC0) ? THC_0 : THC_NONE;
|
||||
s_cfg->ThcAssignment[1] = is_devfn_enabled(PCI_DEVFN_THC1) ? THC_1 : THC_NONE;
|
||||
}
|
||||
|
||||
static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
|
||||
s_cfg->Enable8254ClockGating = !use_8254;
|
||||
s_cfg->Enable8254ClockGatingOnS3 = !use_8254;
|
||||
}
|
||||
|
||||
static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
/*
|
||||
* Legacy PM ACPI Timer (and TCO Timer)
|
||||
* This *must* be 1 in any case to keep FSP from
|
||||
* 1) enabling PM ACPI Timer emulation in uCode.
|
||||
* 2) disabling the PM ACPI Timer.
|
||||
* We handle both by ourself!
|
||||
*/
|
||||
s_cfg->EnableTcoTimer = 1;
|
||||
}
|
||||
|
||||
static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
uint32_t enable_mask = pcie_rp_enable_mask(get_pcie_rp_table());
|
||||
|
||||
for (size_t i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
|
||||
const struct pcie_rp_config *rp_cfg = &config->pcie_rp[i];
|
||||
if (!(enable_mask & BIT(i)))
|
||||
continue;
|
||||
s_cfg->PcieRpL1Substates[i] =
|
||||
get_l1_substate_control(rp_cfg->PcieRpL1Substates);
|
||||
s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR);
|
||||
s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
|
||||
s_cfg->PcieRpHotPlug[i] =
|
||||
!!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
|
||||
s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
|
||||
if (rp_cfg->pcie_rp_aspm)
|
||||
s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
|
||||
}
|
||||
|
||||
s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
|
||||
}
|
||||
|
||||
static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
/* Skip setting D0I3 bit for all HECI devices */
|
||||
s_cfg->DisableD0I3SettingForHeci = 1;
|
||||
|
||||
s_cfg->Hwp = 1;
|
||||
s_cfg->Cx = 1;
|
||||
/* Enable the energy efficient turbo mode */
|
||||
s_cfg->EnergyEfficientTurbo = 1;
|
||||
s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask();
|
||||
/* Un-Demotion from Demoted C1 need to be disable when
|
||||
C1 auto demotion is disabled. */
|
||||
s_cfg->C1StateUnDemotion = !config->disable_c1_state_auto_demotion;
|
||||
s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion;
|
||||
s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion;
|
||||
s_cfg->PkgCStateUnDemotion = !config->disable_package_c_state_demotion;
|
||||
s_cfg->PmcV1p05PhyExtFetControlEn = 1;
|
||||
|
||||
/* Enable/Disable PCH to CPU energy report feature. */
|
||||
s_cfg->PchPmDisableEnergyReport = !config->pch_pm_energy_report_enable;
|
||||
}
|
||||
|
||||
static void fill_fsps_npu_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
s_cfg->NpuEnable = is_devfn_enabled(PCI_DEVFN_NPU);
|
||||
}
|
||||
|
||||
static void fill_fsps_audio_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
if (!is_devfn_enabled(PCI_DEVFN_HDA))
|
||||
return;
|
||||
|
||||
/* Fill MIC privacy settings */
|
||||
s_cfg->PchHdaMicPrivacyHwModeSoundWire0 = 1;
|
||||
s_cfg->PchHdaMicPrivacyHwModeSoundWire1 = 1;
|
||||
s_cfg->PchHdaMicPrivacyHwModeSoundWire2 = 1;
|
||||
s_cfg->PchHdaMicPrivacyHwModeSoundWire3 = 1;
|
||||
s_cfg->PchHdaMicPrivacyHwModeSoundWire4 = 1;
|
||||
s_cfg->PchHdaMicPrivacyHwModeDmic = 1;
|
||||
}
|
||||
|
||||
static void fill_fsps_iax_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
s_cfg->IaxEnable = is_devfn_enabled(PCI_DEVFN_IAA);
|
||||
}
|
||||
|
||||
static void arch_silicon_init_params(FSPS_ARCH2_UPD *s_arch_cfg)
|
||||
{
|
||||
/* Assign FspEventHandler arch Upd to use coreboot debug event handler */
|
||||
if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)
|
||||
&& CONFIG(CONSOLE_SERIAL)
|
||||
&& CONFIG(FSP_ENABLE_SERIAL_DEBUG))
|
||||
s_arch_cfg->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *)
|
||||
fsp_debug_event_handler);
|
||||
|
||||
}
|
||||
|
||||
static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
void (*fill_fsps_params[])(FSP_S_CONFIG *s_cfg,
|
||||
const struct soc_intel_pantherlake_config *config) = {
|
||||
fill_fsps_lpss_params,
|
||||
fill_fsps_cpu_params,
|
||||
fill_fsps_microcode_params,
|
||||
fill_fsps_igd_params,
|
||||
fill_fsps_tcss_params,
|
||||
fill_fsps_chipset_lockdown_params,
|
||||
fill_fsps_xhci_params,
|
||||
fill_fsps_xdci_params,
|
||||
fill_fsps_thermal_params,
|
||||
fill_fsps_irq_params,
|
||||
fill_fsps_pci_ssid_params,
|
||||
fill_fsps_lan_params,
|
||||
fill_fsps_cnvi_params,
|
||||
fill_fsps_pmcpd_params,
|
||||
fill_fsps_thc_params,
|
||||
fill_fsps_8254_params,
|
||||
fill_fsps_pm_timer_params,
|
||||
fill_fsps_pcie_params,
|
||||
fill_fsps_misc_power_params,
|
||||
fill_fsps_npu_params,
|
||||
fill_fsps_audio_params,
|
||||
fill_fsps_iax_params,
|
||||
};
|
||||
|
||||
for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)
|
||||
fill_fsps_params[i](s_cfg, config);
|
||||
}
|
||||
|
||||
/* UPD parameters to be initialized before SiliconInit */
|
||||
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
|
||||
{
|
||||
/* Override settings per board. */
|
||||
struct soc_intel_pantherlake_config *config;
|
||||
FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
|
||||
FSPS_ARCH2_UPD *s_arch_cfg = &supd->FspsArchUpd;
|
||||
|
||||
config = config_of_soc();
|
||||
arch_silicon_init_params(s_arch_cfg);
|
||||
/* Override settings per board if required. */
|
||||
mainboard_update_soc_chip_config(config);
|
||||
soc_silicon_init_params(s_cfg, config);
|
||||
mainboard_silicon_init_params(s_cfg);
|
||||
}
|
||||
|
||||
/*
|
||||
* Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit
|
||||
* This platform supports below MultiPhaseSIInit Phase(s):
|
||||
*
|
||||
* Phase | FSP return point | Purpose
|
||||
* ----- + -------------------------------------+ ------------------------
|
||||
* 1 | After TCSS initialization completed | for TCSS specific init
|
||||
*/
|
||||
void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index)
|
||||
{
|
||||
switch (phase_index) {
|
||||
case 1:
|
||||
/* TCSS specific initialization here */
|
||||
printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n",
|
||||
__FILE__, __func__);
|
||||
|
||||
if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) {
|
||||
const struct soc_intel_pantherlake_config *config = config_of_soc();
|
||||
tcss_configure(config->typec_aux_bias_pads);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Mainboard GPIO Configuration */
|
||||
|
|
@ -18,3 +747,16 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg)
|
|||
{
|
||||
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
|
||||
}
|
||||
|
||||
/* Handle FSP logo params */
|
||||
void soc_load_logo(FSPS_UPD *supd)
|
||||
{
|
||||
efi_uintn_t logo, blt_size;
|
||||
uint32_t logo_size;
|
||||
|
||||
fsp_convert_bmp_to_gop_blt(&logo, &logo_size,
|
||||
&supd->FspsConfig.BltBufferAddress,
|
||||
&blt_size,
|
||||
&supd->FspsConfig.LogoPixelHeight,
|
||||
&supd->FspsConfig.LogoPixelWidth);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue